• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.96-99
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• 2014

In high-${\kappa}$/metal-gate (HK/MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) at 45-nm and below, the metal-gate material consists of a number of grains with different grain orientations. Thus, Monte Carlo (MC) simulation of the threshold voltage ($V_{TH}$) variation caused by the workfunction variation (WFV) using a limited number of samples (i.e., approximately a few hundreds of samples) would be misleading. It is ideal to run the MC simulation using a statistically significant number of samples (>~$10^6$); however, it is expensive in terms of the computing requirement for reasonably estimating the WFV-induced $V_{TH}$ variation in the HK/MG MOSFETs. In this work, a simple matrix model is suggested to implement a computing-inexpensive approach to estimate the WFV-induced $V_{TH}$ variation. The suggested model has been verified by experimental data, and the amount of WFV-induced $V_{TH}$ variation, as well as the $V_{TH}$ lowering is revealed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.123-128
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• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• Journal of IKEEE
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• v.24 no.3
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• pp.853-858
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• 2020

This paper proposes a 2-ch DC-DC converter for OLED display with immunity against RF noise inserted from communication device. For RF signal immunity, an input voltage variation reduction circuit that attenuates as much as the input voltage variation is embedded. The boost converter for positive voltage V_POS operates in SPWM-PWM dual mode and has a dead time controller to increase power efficiency. The inverting charge pump for negative voltage V_NEG is a 2-phase scheme and operates in PFM using VCO to reduce output ripple voltage. Simulation results using 0.18 ㎛ BCDMOS process show that the overshoot and undershoot of the output voltage decrease from 10 mV to 2 mV and 5 mV, respectively. The 2-ch DC-DC converter has power efficiency of 39%~93%, and the power efficiency of the boost converter is up to 3% higher than the conventional method without dead time controller.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.169-175
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• 2006

This study investigated variation leakage current maximum value and waveform considering applied voltage phase angel by simulating three environmental conditions, such as fog, salt fog, and kaolin contamination .As the result of applied voltage phase angel characteristics, leakage currents presented almost in phases in the early stage regardless of environmental conditions just after applying the voltage, and the phase of leakage currents certain phase lags for the discharge of the applied voltage when surface discharges occurred due to the continuous environmental contamination. In addition, the difference in phase significantly increased according to the intensity of discharges. The change in distortion rates according to the environmental contamination presented a nearly same level just after applying the voltage. The distortion rate of third harmonic for the fundamental wave presented by the order of fog>salt fog>kaolin when surface discharges occurred due to the applied voltage for certain continued periods. In the case of the fog and salt fog, the scale of spectrums decreased according to the increase in frequencies from the results of the analysis of high frequencies. In addition, the even number frequency presented a relatively large level compared to the odd number frequency under the kaolin contamination.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.5
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• pp.328-335
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• 2018

An energy management method of DC microgrids using voltage compensation term is proposed in this study. Droop control is often implemented to operate the DC microgrid. However, the droop control necessarily generates voltage variation. Energy flow is also difficult to control because the droop control mainly focuses on proportional load sharing. To solve these problems, the voltage compensation term based on the low-bandwidth communication is used to determine the operating band of the converter. Energy management and voltage variation minimization can be achieved by judging the operating band according to the magnitude of voltage compensation term. The validity of the proposed method is verified by simulation and experiments.

• Journal of Environmental Science International
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• v.23 no.9
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• pp.1601-1608
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• 2014

Plasma reactor was used for the inactivation of Phytophthora capsici which is phytophthora blight pathogen in aquiculture. Effects of first voltage, second voltage, air flow rate, pH, incubation water concentration were examined. At the low $1^{st}$ voltage, under 80 V, the lag phase was noticed within 30 sec, however, it was not shown over 100 V. The variation of optimum operation condition was not shown by the variation of microorganisms. However, the inactivation rate was different by the variation of species of microorganisms. The inactivation rate and efficiency were increased by the increase of $2^{nd}$ voltage. The highest initial inactivation rate was shown at pH 3 and the rate was decreased by the increase of pH. The inactivation rate increased by the increase of air flow rate, however, it was shown as similar at the rate of 4 L/min and 5 L/min. The inactivation rate was distinctly decreased at the three times concentration of incubation solution comparing at the distilled water and basic incubation solution.

• ETRI Journal
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• v.36 no.2
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• pp.321-324
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• 2014

This letter describes a two-phase clock oxide thin-film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART-SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from -4 V to 5 V at a line time of $5{\mu}s$. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively -12.6 dB and -26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16-stage shift registers at $V_{TH}=-1.56V$, compared to 11.5 mW for the conventional circuits.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.1
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• pp.100-105
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• 2010

This paper describes a capacity of distributed generation which will be interconnected at low voltage distribution systems. In order to set the capacity of distributed generation, a voltage variation of distribution system is considered. Besides, the capacity of distributed generation is classified according to a capacity of pole transformer and loads. The system constructions in this paper are analyzed by using PSCAD/EMTDC. In the immediate future, it is expected to increase the installation of New and renewable energy systems which are generally interconnected to distribution power systems in the form of distributed generations like photovoltaic system, wind power and fuel cell. So the study of this kind would be needed to limit the capacity of distributed generation.

• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.67-69
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• 2004

ZnO varistor ceramics which were fabricated with variation of added of 0.01, 0.02, 0.03, 0.05, 0.1mol% $Nb_2O_5$ sintered at $1150^{\circ}C$. In the specimen added 0.05mol% $Nb_2O_5$, sintered density was $5.87g/cm^3$ and electrical properties were superior to any other components. The nonlinear coefficient was 75, and clamping voltage ratio was 1.40. And, endurance surge current in the specimen added 0.05mol% $Nb_2O_5$ was $6500A/cm^2$, and deviation of varistor voltage was -1.7%. As P.C.T and T.C.T environment test were succeed in all specimens, and deviation of varistor voltage in the specimen added 0.3mol% $Nb_2O_5$ was -0.81%. All specimens showed a good leakage current property in the High Temperature Continuous Load Test for 1000hr, at $85^{\circ}C$, and variation rate of the varistor voltage was -1.71%.