• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 추계학술대회 논문집 전력기술부문
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• pp.57-59
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• 2007

When onsite power is supplied from grid due to electrical transient in NPP, the effect of the nuclear plant risk will be increased by the change of grid performance. It is important to analyze the effect for bus voltage of onsite according to grid reliability. Therefore, we analytically accomplish the effect for bus voltage by electrical transient in KSNP.

• 전기학회논문지
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• 제59권9호
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• pp.1523-1529
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• 2010

This paper describes the distribution power system econimical PQMS(Power quality monitoring system) of Utility. Recently, the korea power quality standard has been established based on the IEC Std. By IEC Std., the power quality assessment point is measured in PCC(Point of common coupling). In this case, the utility has to construct PQM system in all customer PCC point and the PQ meter cost would be very high in order to acquire the suitable data. Also the distribution system would be encounter the communication overload problem due to the huge data. Accordingly the utilities could not apply to PQM system in the distribution power system by the cost and communication problem. In this paper, the proposed economical PQMS has the voltage and current signal reiteration function and FFT operation function is transferred the server. Also the voltage and current measurement channels are minimized by a classified substation construction.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.609-611
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• 2006

This paper describes a CMOS sub-bandgap reference using Pseudo-Resistors which can be widely used in flash memory, DRAM, ADC and Power management circuits. Bandgap reference circuit operates weak inversion for reducing power consumption and uses Pseudo-Resistors for reducing the chip area, instead of big resistor. It is implemented in 0.35um Standard 1P4M CMOS process. The temperature coefficient is 5ppm/$^{\circ}C$ from $40^{\circ}C$ to $100^{\circ}C$ and minimum power supply voltage is 1.2V The core area is 1177um${\times}$617um. Total current is below 2.8uA and output voltage is 0.598V at $27^{\circ}C$.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2000년도 춘계종합학술대회
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• pp.489-492
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• 2000

This paper describes a new transient voltage suppressor(TVS) with a low insertion loss and a very wide frequency bandwidth to protect antenna circuit from transient voltages. Conventional protection devices have some problems such as low frequency bandwidth and high insertion loss. In order to improve these limitations, a coaxal type TVS, which consists of a gas tube is developed. The performance of the proposed transient voltage suppressor is tested by using a combination surge generator specified in IEC 61000-4-5 standard and by using a network analyzer of 40 MHz ∼ 5GHz bandwidth. From the experimental results, it is confirmed that the proposed TVS has an enough protection performance in low insertion loss and in wide frequency bandwidth

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.476-477
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• 2008

In this paper, high voltage DC- DC boost converters by stacked structure of power transistors are proposed. These stacked power transistors are tolerant to output voltage higher than the process limit for individual CMOS transistors. The proposed circuits were designed in a standard 3.6V, $0.13{\mu}m$.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.585-586
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• 2008

In this paper, a novel beta-multiplier reference current source circuit for the 800mV power-supply voltage is presented. In order to cope with the narrow input common-mode range of the OpAmp in the reference circuit, shunt resistive voltage divider branches were deployed. High gain OpAmp was designed to compensate intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18um CMOS process with nominal Vth of 420mV and -450mV for nMOS and pMOS transistor respectively. The total power consumption including OpAmp is less than 50uW.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(2)
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• pp.1002-1007
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• 2003

A new driving circuit for the SPSS (Single-Pulse Soft-Switching) PFC converter is proposed. The switching device of a SPSS converter switches once In every half cycle of an AC commercial power source. Therefore, it can be solved many problems caused by the high frequency operation. The proposed SPSS converter achieves the soft-switching operation and the EMI noise can be reduced. The resonant capacitor voltage supplies to the resonant inductor even if the input AC voltage is the vicinity of zero cross voltage. Then, the power factor and input current waveform can be improved without delay time. A new driving circuit achieves the operation of SPSS converter by one switching drive circuit. The proposed converter can be satisfied the IEC standard sufficiently.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 D
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• pp.787-789
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• 1997

This paper presents an algorithm to estimate voltage unbalance which is due to railway demand, and which is most troublesome to polyphase motors. For the sake of accuracy, a circuit analysis procedure is introduced in this algorithm. The circuit analysis procedure enables the algorithm to produce a voltage and current profiles as well as unbalance indices. The proposed algorithm is applied to the test system(standard AT fed system) for the analyses of unbalance phenomena. The result shows that the algorithm is useful in the field of railway system planning.

• 한국철도학회논문집
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• 제11권3호
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• pp.248-256
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• 2008

본 논문은 고속철도 주변 통신회선에 발생되는 잡음전압의 실체 파악을 통해 전력유도잡음전압이 발생하지 않는 것을 증명하였으며, 국내통신회사 및 전파연구소에서 사용하고 있는 평형도 측정에서의 문제점과 계측 오류를 규명하며 표준 측정회로와 측정 조건을 ITU-T 국제 기준에 맞도록 개정할 것을 제안한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.347-350
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• 2000

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.