• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.11
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• pp.622-627
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• 2002

The power comparison techniques have implemented power measurements, in which a power comparator is used to balance ac against a dc power obtained from known values. The developed power standard system using the comparison techniques consists of dc sources, ac source, control switches, resistive voltage dividers, resistive shunts and a power comparator. The total uncertainty of the power standard system was proved by analysis of the component instruments. Its expanded(k=2) uncertainty is evaluated to be less than 30 uW/VA at unit power factor and 42 uW/VA at power factor 0.5

• Journal of IKEEE
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• v.12 no.1
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• pp.34-42
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• 2008

This paper proposes a new on-chip voltage down converter(VDC), which employs a new reference voltage generator(RVG). The converter adopts a temperature-independence reference voltage generator, and a voltage-up converter. The architecture of the proposed VDC has a high-precision, and it was verified based on a 0.25${\mu}m$ 1P5M standard CMOS technology. For 2.5V to 1.0V conversion, the RVG circuit has a good characteristics such as temperature dependency of only 0.2mV/$^{\circ}C$, and the voltage-up circuit has a good voltage deviation within ${\pm}$0.12% for ${\pm}$5% variation of supply voltage VDD. The output voltage is stabilized with ${\pm}$1mV for load current varying from 0 to 100mA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.664-670
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• 2015

A four-times-VDD switch that supports high and low voltage mode operations is demonstrated in a generic 65 nm logic process. The proposed switch shows the robust operation for supply voltages ranging from VDD to $4{\times}VDD$. A cascaded voltage switch and a voltage doubler based charge pump generate the intermediate supply voltage levels required for the proposed high voltage switch. All the high voltage circuits developed in this work can be implemented using standard logic transistors without being subject to any voltage overstress.

• Journal of Electrical Engineering and Technology
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• v.13 no.4
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• pp.1663-1672
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• 2018

In recent times, gas insulated medium voltage (MV) circuit breakers (CB) form a vital component in power system network, considering its advantages such as reduced size and safety margins. Gas insulation characteristics of circuit breakers are generally measured by lightning impulse (LI) test according to IEC standard 60060-1 as a factory routine test. Considering the environmental issues of $SF_6$ gas, many research works are being carried out towards the mixture of $SF_6$ gases for high voltage insulation applications. However, few reports are only available regarding the LI withstand and streamer propagation characteristics (at both positive and negative polarity of waveform) of $SF_6/N_2$ gas mixture insulated medium voltage circuit breakers. In this paper, positive and negative polarity LI tests are carried out on 22 kV medium voltage circuit breaker filled with $SF_6/N_2$ gas mixture at different gas pressures (1-5 bar) and at different gas mixture ratios. Important LI parameters such as breakdown voltage, streamer velocity, time to breakdown and acceleration voltage are evaluated with IEC standard LI ($1.2/50{\mu}s$) waveform. Weibull distribution analysis of LI breakdown voltage data is carried out and 50% probability breakdown voltage, scale parameter and shape parameter are evaluated. Results illustrate that the $25%SF_6+75%N_2$ gas filled insulation considerably enhances the LI withstand and breakdown strength of MV circuit breakers. LI breakdown voltage of circuit breaker under negative polarity shows higher value when compared with positive polarity. Results show that maintaining the gas pressure at 0.3 MPa (3 bar) with 10% $SF_6$ gas mixed with 90% $N_2$ will give optimum lighting impulse withstand performance of 22 kV MV circuit breaker.

• Proceedings of the KIEE Conference
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• 2007.11b
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• pp.18-20
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• 2007

A coupling capacitor voltage transformer (CCVT) is used in an extra high voltage power system to obtain the standard low voltage signal for protection and measurement. To suppress the effects of ferro-resonance more effectively, a three winding CCVT is used. This paper proposes an algorithm for compensating the secondary voltage of the three winding CCVT. With the secondary voltage of the three winding CCVT, the secondary and tertiary currents are obtained; the primary winding current is obtained by considering non-linear characteristics of the core; the voltage across the capacitor and the inductor are calculated and then added to the measured voltage to compensate the secondary voltage. Test results indicate that the algorithm can reduce the errors of the three winding CCVT significantly.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.4
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• pp.78-85
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• 2006

A person's body resistance in the waterpark, public bath and similar places is much lower than any other places due to effect of water. So low voltage may create a shock hazard for the human body in case of leakage or fault currents from lighting unit etc. We researched the related regulations which are internal standards, NEC, IEC and investigated the actual conditions for the prevention of electric shock due to lighting units in the waterpark, public bath and similar places. As a results internal standard is obscure as compared with NEC, IEC which is the limit of application and distinction of environment condition. And then internal standard's using voltage is higher than NEC, IEC in filed of water. Studies show that internal standard should be revision that raise the installation height of lighting unit, mark IP level surface of lighting unit and limit using voltage to line-to-line voltage

• ETRI Journal
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• v.38 no.2
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• pp.272-279
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• 2016

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.214-218
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• 2008

Because on the high-tension underground distribution line of an electric railway high voltage XLPE Cable two or three circuits between railway stations with a standard as receiving transformer facilities are established at a $30km{\sim}50km$ interval, reactive power in which the phase of a current is larger than that of a voltage is supplied when trains are not working, so when there are no loading or low loading as night. Due to the long-distance trend of the underground distribution system on an alternating current railway distribution line, the terminal voltage of a transformer is over the standard voltage, and after all, commercial cycle overvoltage is continued. To solve this problem, the shunt reactor is installed in middle of power distribution lines to maintain receiver voltage meted under the allowance regulation through control of the reactive power. Also, in case that the thickness of single cable is over $60mm^2$ and length of line is about over 30km, a circuit breaker is broken by shorting shunt ability of charging current in excess of shunt current(31.5A.rms). Therefore, this thesis presents installing the location of shunt reactor for quantitative analysis by using optimum algorism for compensation and control of the charging current.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.58-65
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• 2015

This paper presents the design of an implantable stimulation IC intended for neural prosthetic devices using $0.18-{\mu}m$ standard CMOS technology. The proposed single-channel biphasic current stimulator prototype is designed to deliver up to 1 mA of current to the tissue-equivalent $10-k{\Omega}$ load using 12.8-V supply voltage. To utilize only low-voltage standard CMOS transistors in the design, transistor stacking with dynamic gate biasing technique is used for reliable operation at high-voltage. In addition, active charge balancing circuit is used to maintain zero net charge at the stimulation site over the complete stimulation cycle. The area of the total stimulator IC consisting of DAC, current stimulation output driver, level-shifters, digital logic, and active charge balancer is $0.13mm^2$ and is suitable to be applied for multi-channel neural prosthetic devices.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.