• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.3
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• pp.165-169
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• 2012

Power semiconductor devices are widely used as high voltage applications to inverters and motor drivers, etc. The blocking voltage is one of the most important parameters for power semiconductor devices. And cause of junction curvature effects, the breakdown voltage of the device edge and device unit cells was found to be lower than the 'ideal' breakdown voltage limited by the semi-infinite junction profile. In this paper, Propose the methods for field ring design by DOE (Design of Experimentation). So The field ring can be improve for breakdown voltage and optimization.

• Journal of Welding and Joining
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• v.33 no.4
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• pp.24-29
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• 2015

The current waveform was analysed to monitor the weld quality in real time process. The acquired current waveform was discretely analysed for the top and bottom limits of peaks as well as the pulse frequency measurement. Fast Fourier Transform was implemented in the program to monitor the pulse frequency in real time. The developed algorithm or program was tested for the validation purpose. The cross-section of weld profile was compared to the current waveform profile to correlate the monitored signal and the actual parts. Pulse frequency was also used as auxiliary tool for the quality monitoring. Based on the results, it was possible to evaluate the quality of welding by measure the current waveform profile and frequency measurement.

• Journal of the Korean Vacuum Society
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• v.8 no.4A
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• pp.476-481
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• 1999

Characteristics of platinum dry etching were investigated in a cryogenic magnetized inductively coupled plasma (MICP). The problem with platinum etching is the redeposition of sputtered platinum on the sidewall. Because of the redeposits on the sidewall, the etching of patterned platinum structure produces feature sizes that exceed the original dimension of the PR size and the etch profile has needle-like shape [1]. The main object of this study was to investigate a new process technology for fence-free Pt etching As bias voltage increased, the height of fence was reduced. In cryogenic etching, the height of fence was reduced to 20% at-$190^{\circ}C$ compared with that of room temperature, however the etch profile was not still fence-free. In Ar/$SF_6$ Plasma, fence-free Pt etching was possible. As the ratio of $SF_6$ gas flow is more than 14% of total gas flow, the etch profile had no fence. Chemical reaction seemed to take place in the etch process.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.524-525
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• 2008

에너지 효율이 강조되는 요즘, 전력계통의 손실을 최소화시킬 수 있는 분산전원 최적 출력 운전은 에너지 효율 향상에 도움을 줄 것이다. 본 논문에서는 다수의 집중부하를 갖고 있는 방사형 배전계통에 분산전원이 연계됐을 때를 가정하였고 계통 해석을 위해 Dist Flow 방법을 이용하여 계통의 조류계산을 하였다. 분산전원의 최적 출력식을 증명을 통해 도출하였고 시뮬레이션 프로그램 PSCAD /EMTDC으로 검증하여 보았다. 또한 최적 출력을 통해서 전압 profile이 향상되는 것을 볼 수 있었다.

• Journal of Welding and Joining
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• v.17 no.6
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• pp.46-52
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• 1999

The auxiliary gas-shielded MAG (AMAG) process, which was devised to provide an argon-rich shielding environment using small amount of argon gas, was investigated experimentally to figure out its effects on metal transfer and weld quality. Proper conditions for the AMAG process including the argon gas ratio, position and direction of the auxiliary nozzle were determined experimentally. Performance of the AMAG process was compared with that of the double gas-shielded MAG(DMAG) and MAG processes by monitoring the bead profile, current and voltage waveforms. The AMAG process was found to provide better bead profile, more stable arc and wider operating range of spray transfer mode compared with the DMAG process. In general, performance of the AMAG process using the argon ratio of 30% was comparable to that of the MAG process using 80% argon and 20% CO₂ gas.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.212-212
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• 2010

최근 차세대 반도체 메모리 소자로 대두된 magnetic random access memory(MRAM)에 대한 연구가 활발히 진행되고 있다. 특히 MRAM의 magnetic tunnel junction(MTJ) stack을 구성하는 자성 재료의 건식 식각에 대한 연구에서는 좋은 profile을 얻고, 재층착의 문제를 해결하기 위한 노력이 계속해서 진행되고 있다. 본 연구에서는 photoresist(PR)과 Ti 하드 마스크로 패턴 된 배리어(barrier) 층인 MgO 박막의 식각 특성을 유도결합 플라즈마를 이용한 고밀도 반응성 이온 식각(inductively coupled plasma reactive ion etching-ICPRIE)을 통해서 연구하였다. PR 및 Ti 마스크를 이용한 자성 박막들은 HBr/Ar, HBr/$O_2$/Ar 식각 가스의 농도를 변화시키면서 식각되었다. HBr/Ar 가스를 이용 식각함에 있어서 좋은 식각 조건을 얻기 위한 parameter로서 pressure, bias voltage, rf power를 변화시켰다. 각 조건에서 Ti 하드마스크에 대한 터널 배리어층인 MgO 박막에 selectivity를 조사하였고 식각 profile을 관찰하였다. 식각 속도를 구하기 위해 alpha step(Tencor P-1)이 사용되었고 또한 field emission scanning electron microscopy(FESEM)를 이용하여 식각 profile을 관찰함으로써 최적의 식각 가스와 식각 조건을 찾고자 하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.242-249
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• 2011

The proposed converter has easy device selection for high step-up and high power applications since boost half bridge and voltage doubler cells are connected, respectively, in parallel and series in order to increase output power and voltage. Especially, optimized design of high frequency transformers is possible owing to reduced turn ratio and eliminated dc offset, and distributed power through three cores is beneficial to low profile and thermal distribution. The proposed converter does not necessitate start-up circuit and additional clamp circuit due to the use of whole duty range between 0 and 1 and is suitable for applications with wide input voltage range. Also, high efficiency can be achieved since ZVS turn on of switches are achieved in wide duty cycle range and ZCS turn on and off of diodes are achieved. The proposed converter was validated through 5 kW prototype.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.11
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• pp.601-610
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• 2002

Intra-task voltage scheduling (IntraVS), which adjusts the supply voltage within an individual task boundary, is an effective technique for developing low-power applications. In this paper, we propose a novel intra-task voltage scheduling algorithm for hard real-time applications based on average-case execution time. Unlike the conventional IntraVS algorithm where voltage scaling decisions are based on the worst-case execution cycles, tile proposed algorithm improves the energy efficiency by controlling the execution speed based on average-case execution cycles while meeting the real-time constraints. The experimental results using an MPEG-4 decoder program show that the proposed algorithm reduces the energy consumption by up to 34% over conventional IntraVS algorithm.

• 한국전기화학회:학술대회논문집
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• 2004.10a
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• pp.29-29
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• 2004

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.664-667
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• 2011

In this paper, threshold voltage characteristics have been analyzed as one of short channel effects occurred in double gate(DG)MOSFET to be next-generation devices. The Gaussian function to be nearly experimental distribution has been used as carrier distribution to solve Poisson's equation, and threshold voltage has been investigated according to projected range and standard projected deviation, variables of Gaussian function. The analytical potential distribution model has been derived from Poisson's equation, and threshold voltage has been obtained from this model. Since threshold voltage has been defined as gate voltage when surface potential is twice of Fermi potential, threshold voltage has been derived from analytical model of surface potential. Those results of this potential model are compared with those of numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with numerical model, the threshold voltage characteristics have been considered according to the doping profile of DGMOSFET.