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A Dynamic Voltage Scaling Algorithm for Low-Energy Hard Real-Time Applications using Execution Time Profile  

신동군 (서울대학교 전기 컴퓨터 공학부)
김지홍 (서울대학교 전기 컴퓨터 공학부)
Abstract
Intra-task voltage scheduling (IntraVS), which adjusts the supply voltage within an individual task boundary, is an effective technique for developing low-power applications. In this paper, we propose a novel intra-task voltage scheduling algorithm for hard real-time applications based on average-case execution time. Unlike the conventional IntraVS algorithm where voltage scaling decisions are based on the worst-case execution cycles, tile proposed algorithm improves the energy efficiency by controlling the execution speed based on average-case execution cycles while meeting the real-time constraints. The experimental results using an MPEG-4 decoder program show that the proposed algorithm reduces the energy consumption by up to 34% over conventional IntraVS algorithm.
Keywords
dynamic voltage scaling; low-power; real-time;
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1 I. Hong, G. Qu, M. Potkonjak, and M. B. Srivastava. Synthesis techniques for low-power hard real-time systems on variable voltage processor. In Proc. of the 19th IEEE Real-Time Systems Symposium, pp. 178-187, 1998   DOI
2 Y. Shin and K. Choi. Power conscious fixed priority scheduling for hard real-time systems. In Proc. of the 36th Design Automation Conference, pp. 134-139, 1999   DOI
3 D. Shin, J. Kim, and S. Lee. Intra-task voltage scheduling for low-energy hard real-time applications. IEEE Design and Test of Computers, vol. 18, no. 2, pp. 20-30, 2001   DOI   ScienceOn
4 S.-S. Lim, Y. H. Bae, G. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, K. Park, and C. S. Kim. An accurate worst case timing analysis for RISC processors. IEEE Transactions on Software Engineering, vol. 21, no. 7, pp. 593-604, 1995   DOI   ScienceOn
5 T. Ball and J. R. Larus. Using paths to measure, explain, and enhance program behavior. IEEE Computer, vol. 33, no. 7, pp. 57-65, 2000   DOI   ScienceOn
6 P. Puschner and R. Nossal. Testing the results of static worst-case execution-time analysis. In Proc. of the 20th IEEE Real-Time Systems Symposium, pp. 134-143, 1998   DOI
7 S. Lee and T. Sakurai. Run-time voltage hopping for low-power real-time systems. In Proc. of the 37th Design Automation Conference, pp. 806-809, 2000
8 T. Sakurai and A. Newton. Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas. IEEE Journal of Solid State Circuits, vol. 25, no. 2, pp. 584-594, 1990   DOI   ScienceOn
9 F. Yao, A. Demers, and S. Shenker. A scheduling model for reduced CPU energy. In Proc. of he 36th Annual Symposium on Foundations of Computer Scince, pp. 374-382, 1995   DOI
10 Y. Lee and C. M. Krishna. Voltage-clock scaling for low energy consumption in real-time embedded systems. In Proc. of the 6th International Conferene on Real-Time Computing Systems and Applications, pp. 272-279, 1999   DOI
11 T. Burd and R. Broderson. Processor design for portable systems. Journal of VLSI Signal Processing, vol. 13, no. 2, pp. 203-222, 1996   DOI
12 T. Ishihara and H. Yasuura. Voltage scheduling problem for dynamically variable voltage processors. In Proc. of International Symposium On Low Power Electronics and Desgin, pp. 197-202, 1998
13 T. Ball and J. R. Larus. Efficient path profiling. In Proc. of International Symposium on Microarchitecture, pp. 46-57, 1996   DOI