• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1998년도 추계학술대회
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• pp.165-166
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• 1998

A multi-parameter neuro muscular electrical simulator (NMES) system was developed to be used to find the optimal parameter condition in obtaining maximum muscle power and minimal fatigue. Since the performance of NMES is mainly determined by the characteristic of its output-stage circuit, we implemented 3 different circuits and compared output characteristics of them. Three amplifier circuits are; 1) a resonant switching converter, 2) a linear amplifier with a transformer, and 3) a step-up DC/DC converter with a high-voltage linear amplifier. Experimental results showed that the step up DC/DC converter with a high-voltage linear amplifier has the best performance.

• Journal of electromagnetic engineering and science
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• 제14권4호
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• Journal of Advanced Marine Engineering and Technology
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• 제32권8호
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• 한국정보통신학회논문지
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• 제11권1호
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• pp.83-88
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• 2007

MOSFET 트랜지스터의 전기적인 특성 변화에 따른 Class-E RF 전력 증폭기의 신뢰성 특성을 분석하였다. Class-E 전력 증폭기에서 MOSFET는 높은 효율을 얻기 위해 스위치로 동작하며, 이로 인해 MOSFET가 off 되었을 때 드레인 단자에 높은 전압 신호가 발생한다. 회로가 동작함에 따라 높은 전압의 스트레스로 인하여 MOSFET의 문턱 전압은 증가하고 전자의 이동도는 감소하여 MOSFET의 드레인 전류는 감소하게 된다. Class-E 전력 증폭기에서 MOSFET의 전류가 감소하면 전력 효율 및 출력 전력은 감소하게 된다. 그러나 class-E 전력증폭기에서 작은 부하 인덕터를 사용할 경우 큰 인덕터를 사용하는 경우에 비 해 신뢰성 특성을 향상시킬 수 있다. 1mH의 부하 인덕터를 사용한 경우 $10^{7}$초 후에 드레인 전류는 46.3%가 감소하였으며, 전력 효율은 58%에서 36%로 감소하였다. 그러나 1nH의 부하 인덕터를 사용한 경우 드레인 전류는 8.89%, 전력 효율 59%에서 55%로 감소하여 우수한 신뢰성 특성을 보여주었다.

• Journal of Electrical Engineering and Technology
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• 제3권4호
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• pp.566-570
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• 2008

Vertical nanowire SGFETs(Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10nm channel length and a 2nm channel radius. The amplifier dissipates $5{\mu}W$ power and provides 5THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40dBm and -52dBm, respectively, and the 3rd order intermodulation is -24dBm for a two-tone input signal with 10mV amplitude and 10GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2009년도 춘계학술대회
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• pp.678-681
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• 2009

본 논문에서는 자체 바이어스가 되는 Folded Cascode CMOS OP Amp를 이용하여 싱글 픽셀 포톤 계수기 회로를 설계하였다. 전압 바이어스 회로가 필요 없으므로 싱글 픽셀의 레이아웃 면적을 줄이고 전류 소모를 줄일 수 있다. 매그나칩 반도체 $0.18{\mu}m$ CMOS 공정을 이용하여 설계된 CSA(Charge Sensitive Amplifier)의 신호 전압은 이론치인 151mV이 근접한 138mV로 simulation되었다. 그리고 싱글 픽셀의 레이아웃 크기는 $100{\mu}m{\times}100{\mu}m$이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.395-398
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• 2004

High-linearity voltage-controlled current sources (VCCSs) circuits for wide voltage-controlled oscillator and automatic gun control were proposed. The VCCS consists of emitter follower for voltage input, two common-base amplifier which their emitter connected for current output, and current mirror which connected the two amplifier for large output current. The VCCS used only five transistors and a resistor without an extra bias circuit. Simulation results show that the VCCS has current output range from 0mA to 300mA over the control voltage range from 1V to 4.8V at supply voltage 5V. The linearity error of output current has less than $1.4\%$ over the current range from 0A to 300mA.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.538-541
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• 1998

This paper describes the development of 5.15ns 32kb asynchronous CMOS SRAM using 0.6.mu.m CMOS technology. The proposed high speed embedded SRAM is realized with optimized control circuit and sense amplifier at a power supply of 3V. Using proposed control circuit, the delay time from address input to wordline 'on' is reduced by 33% and mismatch-insensitive sense amplifier can sense a small difference of bit-line voltage fast and stably.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.309-312
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• 2002

In this paper, we discuss the design of high gain low noise amplifier by using the 0.2sum CMOS technology. A cascode inverter is adopted to implement the low noise amplifier. The proposed cascode inverter LNA is one stage amplifier with a voltage reference and without choke inductors. The designed 2.4GHz LNA achieves a power gain of 25dB, a noise figure of 2.2dB, and power consumption of 255㎽ at 2.5V power supply.

• 한국정보통신학회논문지
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• 제7권1호
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• pp.114-121
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• 2003

본 연구에서는 ISM 밴드의 블루투스 응용을 위한 2단 CMOS E급 전력증폭기를 설계하였다. 제안된 전력증폭기는 2.4GHz의 주파수에서 동작하며 0.35um CMOS기술과 Hspice 툴을 이용하여 설계 및 시뮬레이션 되었고 Mentor 툴을 이용하여 레이아웃되었다. 전력증폭기의 구조는 간단한 2단으로 설계하였다. 첫단에는 입력매칭네트웍과 전압증폭단인 전치증폭기로, 둘째단은 최대효율과 최대전력을 위한 E급 전력증폭단과 출력 매칭네트웍으로 구성하였다 내부단은 가장 간단한 구조의 L구조의 매칭네트웍을 이용하여 제작될 전체칩의 크기를 최소화하였다. 본 연구에서 제안된 전력증폭기는 2.4GHz의 동작주파수와 2.5V의 낮은 공급전압에서 25.4dBm의 출력전력과 약 39%의 전력부가효율을 얻을 수 있었다. 패드를 제외한 칩의 크기는 약 0.9${\times}$0.8(mm2)였다.