• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.3
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• pp.103-110
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• 2008

In this paper, an efficient butterfly structure for 8K/2K-Point Radix-4 FFT algorithm using CORDIC(coordinate rotation digital computer) is proposed. It is shown that CORDIC can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed CORDIC butterfly structure show 36.9% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 8K/2K-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 11.6% cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• The KIPS Transactions:PartC
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• v.17C no.2
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• pp.145-152
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• 2010

In this paper, we first propose a fast division algorithm in GF($2^{163}$) using standard basis representation, and then it is mapped into divider for GF($2^{163}$) with iterative hardware structure. The proposed algorithm is based on the binary ExtendedGCD algorithm, and the arithmetic operations for modular reduction are performed within only one "while-statement" unlike conventional approach which uses two "while-statement". In this paper, we use reduction polynomial $f(x)=x^{163}+x^7+x^6+x^3+1$ that is recommended in SEC2(Standards for Efficient Cryptography) using standard basis representation, where degree m = 163. We also have implemented the proposed iterative architecture in FPGA using Verilog HDL, and it operates at a clock frequency of 85 MHz on Xilinx-VirtexII XC2V8000 FPGA device. From implementation results, we will show that computation speed of the proposed scheme is significantly improved than the existing two approaches.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.639-641
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• 2022

With the increasing of aging population, a lot of researches on monitoring systems for solitary senior citizens are under study. In general, a monitoring system provides a monitoring service by computing the information of vision, sensors, and measurement values on a server. Design considering data security is essential because a risk of data leakage exists in the structure of the system employing the server. In this paper, we propose a intelligent monitoring system for solitary senior citizens with vision-based security architecture. The proposed system protects privacy by ensuring high security through an architecture that blocks communication between a camera module and a server by employing an edge AI module. The edge AI module was designed with Verilog HDL and verified by implementing on a Field Programmable Gate Array (FPGA). We tested our proposed system on 5,144 frame data and demonstrated that a dangerous detection signal is generated correctly when human motion is not detected for a certain period.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.600-602
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• 2021

With the development of the mobile industry and growing interest in artificial intelligence (AI) technology, a lot of research for AI processors which applicable to embedded systems is under study. When implementing AI to embedded systems, the design should be considered the restriction of resource and power consumption. Moreover, it is efficient to include a dedicated hardware accelerator in order to complement the low computational performance of the embedded system. In this paper, we propose an stand-alone embedded AI processor. The proposed AI processor includes a hardware accelerator that is dedicated to the distance-based AI algorithm and a general-purpose MCU that supports flexible programmability for application to various embedded systems. The AI processor was designed with Verilog HDL and verified by implementing on Field Programmable Gate Array (FPGA).

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.50-56
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• 2016

This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.381-384
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• 2006

PDP is watched as a wall-mounted flat displayer for merits, such as ability to visual maximize and natural color reproduction. But it is more necessary to research video quality why PDP is competing with another displayer. This paper is explaned HDL software architecture implementaion for PDP test-bed module and producing board using FPGA to research 42" PDP video quality.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.530-533
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• 1999

컴퓨터나 각종 전산망의 정보를 보호하기 위해서 가장 안전한 수단은 정보의 직접적인 보호라고 할 수 있는데, 정보사회로 갈수록 지적 재산(IP ; Intellectual Property)이나 기타 다른 중요한 정보의 네트워크를 통한 교류가 활성화될 것이다 본 연구에서는 이러한 보호의 대상이 되는 정보를 암호화시킬 수 있는 알고리즘에 대한 HDL(Hardware Description Language) 구현을 목표로 한다. 현재까지 수많은 알고리즘이 개발되어 왔지만 DES(Data Encryption Standard)가 가장 기본적이고 모든 블록 암호 알고리즘의 기본이 되기 때문에 본 논문에서는 DES에 대한 기본적인 구조를 제시하고 그에 대한 Verilog-HDL 구현을 목표로 하였다. HDL로 설계된 회로는 LC-0.35um 표준 셀 라이브러리를 사용한 synopsys 툴을 이용하여 합성되었다. 전체 회로의 동작 주파수는 약 236MHz고 예상되고 초당 15104비트의 데이터를 암호화 시킬 수 있다.

• Proceedings of the Korea Society for Simulation Conference
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• 1999.04a
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• pp.232-236
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• 1999

Codesign 방법론은 하드웨어와 소프트웨어가 공존하는 시스템을 설계할 때 이드의 설계를 각각의 특성에 맞는 방법을 사용함으로써 효율적인 디자인방법을 제공한다. 전체 시스템의 동작 및 성능을 검증하기 위해서는 다른 방법으로 개발된 하드웨어와 소프트웨어를 같이 시뮬레이션해야 하는데 이를 통합시뮬레이션(Co-simulation)이라고 한다. 하드웨어와 소프트웨어를 개발하는 방법이 다르기 때문에 야기되는 통합의 문제점을 해결하기 위하여 DEVS(Discrete Event System Specification)에 기반한 중간단계형태를 통한 변환방법론을 제시하고 이를 사용하여 C++ 모델과 Verilog HDL 모델간의 통합시뮬레이션을 구현함으로써 효용을 보이고자 한다.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.1
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• pp.99-107
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• 2001

In this paper, we implemented memory BIST circuit based on ION march algorithm, and the IEEE 1149.1 has been designed as main controlJer for embedded memory testing. The implemented memory BIST can be used for word-oriented memory since it adopts background data, this is avaliable for word-oriented memory. It is able to detect all stuck-at faults, transition faults, coupling faults, and address decoder faults in the word-oriented memory. Memory BIST and IEEE 1149.1 are described at RTL level in Verilog-HDL, and synthesized with the Synopsys. The synthesized circuits are fully velified using VerilogXL and memory cell generated by memory compiler.