• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.1
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• pp.11-19
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• 2020

IoT has been consistently used in various fields such as smart home, wearables, and healthcare. Since IoT devices are small terminals, relatively simple wireless communication protocols such as IEEE 802.15.4 and ISO 18000 series are used. In this paper, we designed the 802.15.4q 2.4 GHz TASK physical layer. Physical protocol data unit of TASK supports bit-level interleaving and shortened BCH encoding. It is spread by unique ternary sequences. There are four spreading factors to choose the data rate according to the communication channel environment. The TASK physical layer was designed using verilog-HDL and verified through the loop-back test of the transceiver. The designed TASK physical layer was implemented in a fpga and tested using MAXIM RFICs. The PER was about 0% at 10 dB SNR. It is expected to be used in small, low power IoT applications.

• Journal of Digital Contents Society
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• v.6 no.3
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• pp.169-174
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• 2005

In this paper we propose efficient design and implementation of JPEG image display board that can display JPEG image on TV. we used NAND Flash Memory to save the compressed JPEG bit stream and video encoder to display the decoded JPEG mage on TV. Also we convert YCbCr to RGB to super impose character on JPEG image. The designed B/D is implemented using FPGA.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.106-111
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• 2020

In this paper, we propose the non-contact gesture recognition system and algorithm using proximity-based sensors. The system uses four IR receiving photodiode embedded on a single chip and an IR LED for small area. The goal of this paper is to use the proposed algorithm to solve the problem associated with bringing the four IR receivers close to each other and to implement a gesture sensor capable of recognizing eight directional gestures from a distance of 10cm and above. The proposed system was implemented on a FPGA board using Verilog HDL with Android host board. As a result of the implementation, a 2-D swipe gesture of fingers and palms of 3cm and 15cm width was recognized, and a recognition rate of more than 97% was achieved under various conditions. The proposed system is a low-power and non-contact HMI system that recognizes a simple but accurate motion. It can be used as an auxiliary interface to use simple functions such as calls, music, and games for portable devices using batteries.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.208-214
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• 2005

A number of watermark insertion method is proposed for the protection of audio contents such as MP3 music. In this paper, we propose a VLSI architecture that performs embedding watermark to the audio signal based on the scheme that proposed by XUEYAO LI[1]. This architecture is implemented and simulated in Verilog HDL. This watermark embedding method used a visually recognizable binary image. Despite a unit that determines the watermark embedded intensity is removed to archive low complexity of H/W, our experimental results show that watermarked signal is perceptually transparency and robust to several known attacks.

• Proceedings of the IEEK Conference
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• summer
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• pp.285-288
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• 2004

In this paper, we present a design and experiment of PCI Express core verification model. The model targeting Endpoint core based on Verilog HDL is designed by newly-emerging SystemC, which is a new C++ class library based system design approach. In the verification model, we designed and implemented a SystemC host system model which acted as Root Complex and device driver dedicated to the PCI Express Endpoint RTL core. The verification process is scheduled by scenarios which are implemented in host model. We show that the model is useful especially for verifying the RTL model which has dependencies on system software.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.643-644
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• 2006

In this paper, WiBro system which is one of the mobile wireless metropolitan area network systems is presented. WiBro is an OFDMA system which has a sub-channelization process unlike conventional OFDM systems. The sub-channelization is the time consuming processing, so a time-efficient hardware architecture is needed. WiBro RAS(Radio Access Station) demodulator is designed with Verilog HDL, and the gate count is 81k using the $0.18{\mu}m$ processing.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.651-652
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• 2006

In this paper, 4-way data path 128 point pipelined FFT processor with 4-way structure is proposed. The proposed FFT processor has 4-way structure in order to meet data requirement of MB-OFDM system at 132MHz operating frequency. The FFT processor is based on R4MDC and extended to suit 4-way data path. The FFT processor is designed by Verilog HDL and the gate count is about 88k.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.13-14
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• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show 61.02% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 46.1% cell area reduction.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.527-528
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• 2006

In this paper, we propose an IP design and implementation of System on a chip(SoC) for Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) processor using adder-based DA(Adder-based Distributed Arithmetic). To reduced hardware cost and to improve operating speed, the combined DCT/ DWT processor used the bit-serial method and DA module. The transform of coefficient equation result in reduction in hardware cost and has a regularity in implementation. We use Verilog-HDL and Xilinx ISE for simulation and implement FPGA on SoCMaster-3.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.83-88
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• 2015

Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.