• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.673-676
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• 2008

In wireless communications such as Bluetooth, Baseband should be able to minimize the DC bias of the data which passed the modem interface of either transmitter or receiver for the reliability of the circuit and the integrity of the data. The transmitter scrambles the data to send randomly to the error correction block and the receiver recovers the randomly spread data as they have been. To design the whitening block, it is important to select the prime polynomial for the filtering. In this paper, we designed a optimal whitening block using the prime polynomial $g(D)=D^7+D^4+1$ for hardware and area efficiency. The proposed hardware whitening block was described and verified using Verilog HDL and later to be automatically synthesized. The synthesized whitening block operated at 40Mhz normal clock speed of the target baseband microcontroller.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.99-102
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• 2012

An image scaler is a IP used in a image processing block of display devices to adjust image size. Proposed image scaler adopts line memories instead of a conventional method using a frame memory. This method reduced hardware resources and enhanced data precision by using shift operations that number is multiplied by $2^m$ and divided again at final stage for scaling. Also image scaler increased efficiency of IP by using serial divider to calculate parameters by itself. Parameters used in image scaling is automatically produced by it. Suggested methods are designed by Verilog HDL and implemented with Xilinx Vertex-4 XC4LX80 and ASIC using TSMC 0.18um process.

• Journal of IKEEE
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• v.24 no.3
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• pp.783-790
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• 2020

In this paper, the human detecting radar system for indoor security applications is proposed, and its FPGA-based implementation results are presented. In order to minimize the complexity and memory requirements of the computation, the top half of the spectrogram was used to extract features, excluding the feature extraction techniques that require complex computation, feature extraction techniques were proposed considering classification performance and complexity. In addition, memory requirements were minimized by designing a pipeline structure without storing the entire spectrogram. Experiments on human, dog and robot cleaners were conducted for classification, and 96.2% accuracy performance was confirmed. The proposed system was implemented using Verilog-HDL, and we confirmed that a low-area design using 1140 logics and 6.5 Kb of memory was possible.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.7
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• pp.1702-1708
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• 2013

OLED has good efficiency of power consumption by having no power consumption from black color as different with LCD. when it has white color, all RGB pixel should be glowing with high power consumption and that can make it has short life time. This paper suggest the way of low power consumption for OLED panel using adaptive luminance enhancement with color compensation and implement it as hardware. This way which is based on luminance information of input image makes converted luminance value from each pixel in real time. There is with using the basic idea of chromaticity reduction algorithm, showing new algorithm of color correction. And performance of proposed method was confirmed by comparing the conventional method in experiments about 48.43% current reduction. The proposed method was designed by Verilog HDL and was verified by using OpenCV and Windows Program.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1844-1850
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• 2016

The bilateral filter can reduce the noise while preserving details computing the filtering output at each pixels as the average of neighboring pixels. In this paper, we propose a real-time system based on window division. Overall performance is increased due to the parallel architectures which computes five rows in the kernel window simultaneously but with pipelined scheduling. We consider the tradeoff between the filter performance and the hardware cost and the bit allocation has been determined by PSNR analysis. The proposed architecture is designed with verilogHDL and synthesized using Dongbu Hitek 110nm standard cell library. The proposed architecture shows 416Mpixels/s (397fps) of throughput at 416MHz of operating frequency with 132K gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2A
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• pp.202-213
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• 2004

In this paper, we propose a preamble structure and synchronization/channel estimation methods for OFDM-based multiple antenna WLAN systems that have 200Mbps transmit rate. With the proposed preamble structure, multiple antenna WLAN systems are backward-compatible with IEEE 802.11a systems which use the same 5㎓ band and synchronization performance is better than that of single antenna OFDM systems. For channel estimation, the preamble overhead is small and performance degradation by timing synchronization error that causes the critical problem of conventional comb-type multiple antenna channel estimation method also can be minimized by frequency domain phase recovery. Synchronizer and channel estimator for proposed preamble structure are implemented and verified using Verilog HDL. For the system with 4 transmit antennas and 4 receive antennas, about 150K gates are needed for synchronizer and 12K gates for channel estimator.

• Journal of Internet Computing and Services
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• v.11 no.4
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• pp.23-32
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• 2010

In this paper, we first propose the security enhancing of authentication protocol for Hash based RFID tag, and then a digital Codec for RFID tag is designed based on the proposed authentication protocol. The protocol is based on a three-way challenge response authentication protocol between the tags and a back-end server. In order to realize a secure cryptographic authentication mechanism, we modify three types of the protocol packets which defined in the ISO/IEC 18000-3 standard. Thus active attacks such as the Man-in-the-middle and Replay attacks can be easily protected. In order to verify effectiveness of the proposed protocol, a digital Codec for RFID tag is designed using Verilog HDL, and also synthesized using Synopsys Design Compiler with Hynix $0.25\;{\mu}m$ standard-cell library. Through security analysis and comparison result, we will show that the proposed scheme has better performance in user data confidentiality, tag anonymity, Man-in-the-middle attack prevention, replay attack, forgery resistance and location tracking.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.125-131
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• 2010

This paper presents the implementation of a EBCOT TIER-1 for JPEG2000 Encoder. JPEG2000 is new standard for the compression of still image for overcome the artifact of JPEG. JPEG2000 standard is based on DWT(Discrete Wavelet Transform) and EBCOT Entropy coding technology. EBCOT(Embedded block coding with optimized truncation) is the most important technology that is compressed the image data in the JPEG2000. However, EBCOT has the artifact because the operations are bit-level processing and occupy the harf of the computation time of JPEG2000 Compression. Therefore, in this paper, we present modified context extraction method for enhance EBCOT computational efficiency and implemented MQ- Coder as arithmetic coder. The proposed system is implemented by Verilog-HDL, under the condition of TSMC 0.25um ASIC library, gate counts are 30,511EA and satisfied the 50MHz operating condition.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9B
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• pp.939-946
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• 2009

In this paper, we propose a new network ASIP(Application Specific Instruction-set Processor) which was designed for simulation models by a machine descriptions language LISA(Language for Instruction Set Architecture). This network ASIP is aimed for an exclusive engine undertaking packet processing in a router. To achieve the purpose, we added a new necessary instruction set for processing a general ASIP based on MIPS(Microprocessor without Interlock Pipeline Stages) architecture in high speed. The new instructions can be divided into two groups: a classification instruction group and a modification instruction group, and each group is to be processed by its own functional unit in an execution stage. The functional unit was optimized for area and speed through Verilog HDL, and the result after synthesis was compared with the area and operation delay time. Moreownr, it was allocated to the Macro function ana low-level standardized programming language C using CKF(Compiler Known Function). Consequently, we verified performance improvement achieved by analysis and comparison of execution cycles of application programs.