• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.162-168
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• 2011

In this paper, we propose a new Verilog-A current-voltage model for multi-level-cell PCRAMs. This model can describe the PCRAM operation not only in full SET and RESET states but also in the partial resistance states. And, 3 PCRAM operating regions of SET-RESET, Negative Differential Resistance, and strong-ON are unified into one equation in this model thereby any discontinuity that may introduce a convergence problem cannot be found in the new PCRAM model. The percentage error between the measured data and this model is as small as 7.4% on average compared to 60.1% of the previous piecewise model. The parameter extraction which is embedded in the Verilog-A code can be done automatically.

• ETRI Journal
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• v.33 no.1
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• pp.50-59
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• 2011

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.682-684
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• 2007

This paper deals the application of sensor network system to fabricate wireless nodes. This node includes a CPLD(XC2C256), FPGA(XC3S1000) a RF module(Bim-433-F), a Hall Sensor and I also develop the CPLD(EPGA) controlling with Verilog-HDL using ISE. The network was consisst of a PC, a Sink node as a gateway, and three Sensor nodes. This sensor network can reaches 40 m with RF interface using by multi-path network.

• Journal of information and communication convergence engineering
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• v.11 no.2
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• pp.112-117
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• 2013

In order to reuse a register transfer level (RTL)-based IP block, it takes another architectural exploration in which the RTL will be put, and it also takes virtual platforms to develop the driver and applications software. Due to the increasing demands of new technology, the hardware and software complexity of organizing embedded systems is growing rapidly. Accordingly, the traditional design methodology cannot stand up forever to designing complex devices. In this paper, I introduce an electronic system level (ESL)-based approach to designing complex hardware with a derivative of SystemVerilog. I adopted the concept of reuse with higher levels of abstraction of the ESL language than traditional HDLs to design multiplication server farms. Using the concept of ESL, I successfully implemented server farms as well as a test bench in one simulation environment. It would have cost a number of Verilog/C simulations if I had followed the traditional way, which would have required much more time and effort.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.852-855
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• 2003

This paper reports the RFC(Recursive Flow Classification) algorithm that is available on multiple fields. It is easy to be implemented by both software and hardware. For high speed classification of packets, the implementation of RFC is essential by hardware. Hence, in this paper, RFC algorithm is simulated by Verilog-HDL, and it verify the efficiency of the algorithm. The result shows that the algorithm can perform a packet classification within several cycles. It is not only much faster than software implementation but also enough to support OC192c.

• Journal of information and communication convergence engineering
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• v.19 no.4
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1957-1965
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• 2000

본 논문에서는 휴대 멀티미디어 응용을 위한 MDSP(Multimedia Fixed Point DSP) 칩의 내장 메모리 테스트와 기판 수준의 테스트를 지원하기 위해 내장 메모리 테스트를 위한 자체 테스트 기법, 기판 수준의 테스트 지원 및 내장 메모리를 위한 자체 테스트 회로를 제어하기 위한 경계 주사 기법을 구현하였다. 본 논문에서 구현한 기법들은 Verilog HDL을 이용하여 회로들을 설계하였으며, Synopsys 툴과 현대 heb60 라이브러리를 이용하여 합성하였다. 그리고 회로 검증을 위한 시뮬레이터는 Cadence사의 VerilogXL을 사용하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.431-434
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• 2008

The physical OLED analog behavioral model for SPICE simulation has been described using Verilog-A language. The model is based on the carrier-balance between the hole and electron injected through Schottky barrier at anode and cathode. The accuracy of this model was examined by comparing with the results from device simulation.

• Journal of Information Display
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• v.10 no.3
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• pp.101-106
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• 2009

In this study, a physical OLED analog behavior model for SPICE simulation was described using the Verilog-A language. The model was presented through theoretical equations for the J-V characteristics of OLED derived according to the internalcarrier emission equation based on a diffusion model at the Schottky barrier contact, and the mobility equation based on the Pool-Frenkel model. The accuracy of this model was examined by comparing it with the results of the device simulation that was conducted.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.427-428
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• 2008

본 논문에서는 IEEE 802.11 MAC Layer의 Reception, Transmission 검증을 위해 PLI (Programing Language Interface)를 이용한 방법을 제안한다. PLI를 이용한 검증은 시스템 Level의 검증으로써 설계단계에서 문제점을 확인하고 수정할 수 있다. 그러므로 불필요한 개발비의 낭비를 줄일 수 있고 개발 기간 단축의 효과를 거둘 수 있다. 검증을 위해 Mentor Graphics 사의 HDL (Hardware Description Language) 시뮬레이터인 Modelsim 6.1g Version을 사용하고 PLI를 이용하여 검증 환경을 구축한다.