• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.9
• /
• pp.103-109
• /
• 2008

This paper presents the architecture and design of intra prediction circuit for H.264 decoder. There are a total of 17 operational modes in the intra prediction of H.264- nine modes for a luma $4\times4$ block, four modes for a luma $16\times16$ block and four modes for a chroma $8\times8$ block. We extracted common operations included in all prediction modes and defined the common operations unit to perform those operations. The proposed circuit architecture sharing this unit in all prediction modes is systematic from the design point of view and efficient in terms of circuit size.

• Nuclear Engineering and Technology
• /
• v.55 no.4
• /
• pp.1365-1381
• /
• 2023

In this paper, a procedure for evaluating the structural integrity of the PCSG (Printed Circuit Steam Generator) unit block is presented with a simplified FE (finite element) analysis technique by applying the homogenization method. The homogenization method converts an inhomogeneous elastic body into a homogeneous elastic body with same mechanical behaviour. This method is effective when the inhomogeneous elastic body has repetitive microstructures, and thus the method was applied to the sheet assembly among the PCSG unit block components. From the method, the homogenized equivalent elastic constants of the sheet assembly were derived. The validity of the determined material properties was verified by comparing the mechanical behaviour with the reference model. Thermo-mechanical analysis was then performed to evaluate the structural integrity of the PCSG unit block, and it was found that the contact region between the steam header and the sheet assembly is a critical point where large bending stress occurs due to the temperature difference.

• Journal of Broadcast Engineering
• /
• v.21 no.6
• /
• pp.944-956
• /
• 2016

In this paper, we propose a new hardware architecture to generate computer-generated holograms based on the block based calculation method and implement a VLSI (very large scaled integrated circuit) in ASIC (application specific integrated circuit) environment. The proposed hardware has a structure that can produce a part of a hologram in the unit of a block in parallel. After calculating a block of a hologram by using an object point, the calculation is repeated to all object points and intermediate results from them are accumulated to produce a final block of a hologram. Through this structure, we can make various size of holograms with the optimized memory access in real-time operation. The proposed hardware was implemented in the Hynix 0.18um CMOS technology of Magna chip Inc. and has 876,608 gate counts. It can generate complex holograms unlike the previous researches and stably operate in the clock frequency of 200MHz.

• Proceedings of the KSR Conference
• /
• 2011.10a
• /
• pp.2726-2730
• /
• 2011

This paper proposes a CBTC wayside signaling system, which redeems existing track-circuit-based ones by using movement authorities mixed with logical block and moving block. Only one train can be entered into the logical block or the route for existing wayside signaling system. Applying moving block for CBTC system enables the train to get nearer to the preceding one, because its protection mechanism uses train's safe boundary, not fixed block unit. By narrowing the existing route set to switch machine and applying the moving block beyond that area, more than one train can enter into one route area. This paper shows that the efficient train control, i.e. shortening the headway, is possible using the moving block mixed with logical block in wayside signaling system.

• Proceedings of the KIEE Conference
• /
• 2003.11b
• /
• pp.267-270
• /
• 2003

This paper proposes high performance $8{\times}8$ multiplier using current-mode quaternary logic technique. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion), current-mode quaternary logic full-adder block, quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. Also, this multiplier can easily adapted to binary system by the encoder, the decoder. This circuit is simulated under 0.35um standard CMOS technology, 5uA unit current, and 3.3V supply voltage using Hspice.

• Journal of Sensor Science and Technology
• /
• v.23 no.2
• /
• pp.87-93
• /
• 2014

In this paper, we propose a block-based low-power complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a simple pixel structure for power efficiency. This method, which uses an additional computation circuit, makes it possible to reduce the power consumption of the pixel array. In addition, the computation circuit for a block-based CIS is very flexible for various types of pixel structures. The proposed CIS was designed and fabricated using a standard CMOS 0.18 ${\mu}m$ process, and the performance of the fabricated chip was evaluated. From a resultant image, the proposed block-based CIS can calculate a differing contrast in the block and control the operating voltage of the unit blocks. Finally, we confirmed that the power consumption in the proposed CIS with a simple pixel structure can be reduced.

• Journal of Korea Multimedia Society
• /
• v.6 no.7
• /
• pp.1169-1177
• /
• 2003

The blocking effect results from independent coding of each image block and becomes highly visible, especially coded at very low bit rates. In this paper, a blocking effect reduction circuit is designed which is composed of a memory, arithmetic and logic unit, and control block. The circuit is based on a rational open uniform B-spline curve that uses to produce a smooth curve through a set of control points. The weight values and the modified pixel values in a rational open uniform B-spline curve are calculated using arithmetic and logic circuits. The simulation results show that the circuit has excellent performance for ail pattern of the blocking effects.

• Progress in Superconductivity
• /
• v.6 no.1
• /
• pp.7-12
• /
• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.842-846
• /
• 2015

In this study, we propose an algorithm of the method of recovering quickly find the location of the error encountered during separate operations in the functional structure of complex digital circuits by mimicking the self-healing function of the cell. By the digital circuit was divided by 9 function block unit of function, proposes a method that It can quickly detect and recover the error position. It was the detection and recovery algorithms for the error location in the digital circuit of a complicated structure and could extended the number of function block for the $3{\times}3$ matrix structure on the digital circuit.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.11
• /
• pp.2745-2750
• /
• 2015

Abstract should be placed here In this study, we propose an algorithm of the method of recovering quickly find the location of the error encountered during separate operations in the functional structure of complex digital circuits by mimicking the self-healing function of the cell. By the digital circuit was divided by 9 function block unit of function, proposes a method that It can quickly detect and recover the error position. It was the detection and recovery algorithms for the error location in the digital circuit of a complicated structure and could extended the number of function block for the $3{\times}3$ matrix structure on the dital circuit.