• 제목/요약/키워드: ultra-thin silicon wafer

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Ultra Thin 실리콘 웨이퍼를 이용한 RF-MEMS 소자의 웨이퍼 레벨 패키징 (Wafer Level Packaging of RF-MEMS Devices with Vertical feed-through)

  • 김용국;박윤권;김재경;주병권
    • 한국전기전자재료학회논문지
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    • 제16권12S호
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    • pp.1237-1241
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    • 2003
  • In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

다구찌 실험계획법을 이용한 탄소코팅 초박막의 마찰특성 (Friction Properties of Carbon Coated Ultra-thin Film using Taguchi Experimental Design)

  • 안준양;김대은;최진용;신경호
    • 한국정밀공학회지
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    • 제20권4호
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    • pp.143-150
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    • 2003
  • Frictional properties of ultra-thin carbon coatings on silicon wafer were investigated based on Taguchi experimental design method. Sensitivity analysis was performed with normal load, relative humidity, deposition process, and coating thickness as the variables. It was found that despite low thickness, the carbon coating resulted in relatively low friction coefficient. Also, the frictional behavior was affected significantly by humidity and normal load.

실리콘 웨이퍼 위에 제작된 DLPC 지질막의 전기적특성 (Elctrical Properties of DLPC Lipid Membrane Fabricated on the Silicon Wafer)

  • 이우선;김충원;이강현;정용호;김남오;김상용
    • 한국전기전자재료학회논문지
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    • 제11권12호
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    • pp.1115-1121
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    • 1998
  • MLS capacitor with lipid ultra thin films were deposited by Langmuir-Blodgett (LB) method on the silicon wafer. The current versus voltage and capacitance versus voltage relationships are depend on the applied voltage, electrode area and electrode materials. LB films deposited were made of L-$\alhpa$-DLPC, the 1 layer’s thickness of 35${\AA}$ was measured by ellipsometer. And MLS capacitor with different electrode materials, the work function of these materials was investigated to increase the leakage current. The result indicated the lower leakage current and very high saturation value of capacitance was reached within 700-800 pF when the two electrode was Ag. And $\varepsilon$1, $\varepsilon$2 versus photon energy showed good film formation.

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Nb SQUID가 탑재된 초고감도 캔티레버 제작 (Fabrication of Nb SQUID on an Ultra-sensitive Cantilever)

  • 김윤원;이순걸;최재혁
    • Progress in Superconductivity
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    • 제11권1호
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    • pp.36-41
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    • 2009
  • Superconducting quantum phenomena are getting attention from the field of metrology area. Following its first successful application of Josephson effect to voltage standard, piconewton force standard was suggested as a candidate for the next application of superconducting quantum effects in metrology. It is predicted that a micron-sized superconducting Nb ring in a strong magnetic field gradient generates a quantized force of the order of sub-piconewtons. In this work, we studied the design and fabrication of Nb superconducting quantum interference device (SQUID) on an ultra-thin silicon cantilever. The Nb SQUID and electrodes were structured on a silicon-on-insulator (SOI) wafer by dc magnetron sputtering and lift-off lithography. Using the resulting SOI wafer, we fabricated V-shaped and parallel-beam cantilevers, each with a $30-{\mu}m$-wide paddle; the length, width, and thickness of each cantilever arm were typically $440{\mu}m,\;4.5{\mu}m$, and $0.34{\mu}m$, respectively. However, the cantilevers underwent bending, a technical difficulty commonly encountered during the fabrication of electrical circuits on ultra-soft mechanical substrates. In order to circumvent this difficulty, we controlled the Ar pressure during Nb sputtering to minimize the intrinsic stress in the Nb film and studied the effect of residual stress on the resultant device.

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반도체 3차원 칩 적층을 위한 미세 범프 조이닝 기술 (Micro-bump Joining Technology for 3 Dimensional Chip Stacking)

  • 고영기;고용호;이창우
    • 한국정밀공학회지
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    • 제31권10호
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    • pp.865-871
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    • 2014
  • Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

응력 주입 층을 이용한 Kerf-less 웨이퍼링 기술 동향

  • 양현석;엄누시아;김지원;임재홍
    • 세라미스트
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    • 제21권2호
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    • pp.75-82
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    • 2018
  • In the photovoltaics (PV) industry, there were many efforts to reduce the cost of production with high efficiency. The single most important cost factor in silicon technology is the wafer, accounting presently for ~35% of the module cost. it was already shown that the solar cell efficiency can be maintained up to the thickness range of $40-60{\mu}m$. The direct production of ultra-thin silicon wafer is very attractive and numerous different techniques, such as electrochemical process, ion implantation, and epitaxial growth, have been proposed and developed in many academic and industrial laboratories.

Reduction of surface roughness during high speed thinning of silicon wafer

  • Heo, W.;Ahn, J.H.;Lee, N.E.
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.392-392
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    • 2010
  • In this study, high-speed chemical dry thinning process of Si wafer and evolution of surface roughness were investigated. Direct injection of NO gas into the reactor during the supply of F radicals from $NF_3$ remote plasmas was very effective in increasing the Si thinning rate due to the NO-induced enhancement of surface reaction but thinned Si surface became roughened significantly. Addition of Ar gas, together with NO gas, decreased root mean square (RMS) surface roughness of thinned Si wafer significantly. The process regime for the thinning rate enhancement with reduced surface roughness was extended at higher Ar gas flow rate. Si wafer thinning rate as high as $22.8\;{\mu}m/min$ and root-mean-squared (RMS) surface roughness as small as 0.75 nm could be obtained. It is expected that high-speed chemical dry thinning process has possibility of application to ultra-thin Si wafer thinning with no mechanical damage.

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ALD를 이용한 극박막 $HfO_2 /SiON$ stack structure의 특성 평가 (Characterization of $HfO_2 /SiON$ stack structure for gate dielectrics)

  • Kim, Youngsoon;Lee, Taeho;Jaemin Oh;Jinho Ahn;Jaehak Jung
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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    • pp.115-121
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    • 2002
  • In this research we have investigated the characteristics of ultra thin $HfO_2 /SiON$stack structure films using several analytical techniques. SiON layer was thermally grown on standard SCI cleaned silicon wafer at $825^{\circ}C$ for 12sec under $N_2$O ambient. $HfO_2 /SiON$$_4$/$H_2O$ as precursors and $N_2$as a carrier/purge gas. Solid HfCl$_4$was volatilized in a canister kept at $200^{\circ}C$ and carried into the reaction chamber with pure $N_2$carrier gas. $H_2O$ canister was kept at $12^{\circ}C$ and carrier gas was not used. The films were grown on 8-inch (100) p-type Silicon wafer at the $300^{\circ}C$ temperature after standard SCI cleaning, Spectroscopic ellipsometer and TEM were used to investigate the initial growth mechanism, microstructure and thickness. The electrical properties of the film were measured and compared with the physical/chemical properties. The effects of heat treatment was discussed.

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