• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.1
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• pp.1-11
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• 1999

Hyrdogenated amorphous silicon thin film transistors are used as a pixel switching device of TFT-LCDs and very active research works on a-Si:H TFTs are in progress. Further development of the technology based on a-Si:H TFTs depends on the increased understanding of the device physics and the ability to accurately simulate the characteristics of them. A two-dimensional device simulator based on the realistic and flexible physical models can guide the device designs and their optimizations. A non-uniform finite-difference TFT Simulation Program, TFT2DS has been developed to solve the electronic transport equations for a-Si:H TFTs. In TFT2DS, many of the simplifying assumptions are removed. The developed simulator was used to calculate the transfer and output characteristics of a-Si:H TFTs. The measured data were compared with the simulated ones for verifying the validity of TFT2DS. Also the transient behaviors of a-Si:H TFTs were calculated even if the values of the related parameters are not accurately specified.

• Journal of Information Display
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• v.13 no.4
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• pp.179-183
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• 2012

In this paper, a gate driver circuit for In-Ga-Zn-O thin-film transistors (TFTs) driven by only two clock signals is reported. In this circuit, the TFTs are turned off with a negative $V_{GS}$ by the two clock signals. As a result, it works properly and suppresses power consumption increase even though the TFT $V_T$ shifts in the negative direction.

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.252-257
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• 1994

A non-uniform finite-difference Thin Film Transistor Simulation Program (TFTSP) has been developed for hydrogenated amorphous silicon TFTs. TFTSP was developed to remove as many of simplifying assumptions as possible and to provide flexibility in the modeling of TFTs so that different model assumptions may be analyzed and compared. In order to insure its usefulness and versatility as an analytic and design tool it is important for the code to satisfy a number of conditions. However, at the beginning stage of the program development, this paper shows that the code can compute the static terminal characteristics of a-Si:H TFTs under a wide range of bias conditions to allow for comparison of the model with experiment. Some of those comparisons include transfer characteristics and I-V characteristics. TFTSP will be refined to conveniently model the performances of TFTs of different designs and to analyze many anomalous behaviors and factors of a-Si:H TFTs.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.261-264
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• 2007

We developed a non self-aligned poly-silicon TFTs fabrication process at two different temperatures on spin-coated polyimide layer above Si-wafer. After TFTs fabrication, the polyimide layer was mechanically released from the Si-wafer and the devices characteristics were compared. In addition self-heating and hot-carrier induced instabilities were analysed.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.127-133
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• 1996

In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photoresist reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate form both sides of the main gate. The poly-Si channel layer below the offset oxide is protected form the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of oru new device is the offset region due to the offset oxide. our experimental reuslts show that the offset region, due to the photoresist reflow process, has been sucessfully obtained in order to fabricate the offset gated poly-Si TFTs. The maximum ON/OFF ratio occurs at the L$_{off}$ of 1.1${\mu}$m and exceeds 1X10$^{6}$.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1772-1775
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• 2000

We have fabricated poly-Si TFTs by two-step crystallizaton. Poly-Si films have been prepared by furnace annealing(FA) and rapid thermal annealing(RTA) followed by subsequent the post-annealing, excimer laser annealing. The measured crystallinity of RTA and FA annealed poly-Si film is 77% and 68.5%, respectively. For two-step annealed poly-Si film, the crystallinity has been drastically to 87.7% and 86.3%. The RMS surface roughness from AFM results have been improved from 56.3${\AA}$ to 33.5${\AA}$ after post annealing. The measured transfer characteristics of the two-step annealed poly-Si TFTs have been improved significantly for the both FA-ELA and RTA-ELA. Leakage currents of two-step annealed poly-Si TFTs are lower than that of the devices by FA and RTA. From these results, we can describe the fact that the intra-grain defects has been cured drastically by the post-annealing.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.274-277
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• 2000

Thin Film Transistor(TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature(500$^{\circ}C$) Metal-Induced Lateral Crystallization(MILC) furnace annealing and high -temperature (700$^{\circ}C$) rapid thermal annealing leads to the improvement of the material quality The TFTs measured with this two-step annealing material exhibit better characteristics than those obtained by using conventional MILC furnace annealing.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.164.2-164.2
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• 2014

In order to combine advantages of ZnO thin film transistors (TFTs) with a high on-off ratio and graphene TFTs with extremely high carrier mobility, we present a facile methodology for fabricating ZnO thin film/graphene hybrid two-dimensional TFTs. Hybrid TFTs exhibited ambipolar behavior, an outstanding electron mobility of $329.7{\pm}16.9cm^2/V{\cdot}s$, and a high on-off ratio of $10^5$. The ambipolar behavior of the ZnO/graphene hybrid TFT with high electron mobility could be due to the superimposed density of states involving the donor states in the bandgap of ZnO thin films and the linear dispersion of monolayer graphene. We further established an applicable circuit model for understanding the improvement in carrier mobility of ZnO/graphene hybrid TFTs.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.