• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.482-491
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• 2012

In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as heterogeneous gate (HG) dielectric, gate drain underlap (GDU) and asymmetric source/drain doping on the ambipolar behavior is quantified in terms of physical parameters proposed for ambipolarity characterization. Moreover, the impact on the miller capacitance is also taken into consideration since ambipolarity is directly related to reliable logic circuit operation and miller capacitance is related to circuit performance.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.585-593
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• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.224-236
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• 2013

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.

• 진공이야기
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• 제3권3호
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• 한국재료학회지
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• 제30권2호
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• pp.99-104
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• 2020

Recent discoveries of ferroelectric properties in ultrathin doped hafnium oxide (HfO₂) have led to the expectation that HfO₂ could overcome the shortcomings of perovskite materials and be applied to electron devices such as Fe-Random access memory (RAM), ferroelectric tunnel junction (FTJ) and negative capacitance field effect transistor (NC-FET) device. As research on hafnium oxide ferroelectrics accelerates, several models to analyze the polarization switching characteristics of hafnium oxide ferroelectrics have been proposed from the domain or energy point of view. However, there is still a lack of in-depth consideration of models that can fully express the polarization switching properties of ferroelectrics. In this paper, a Zr-doped HfO₂ thin film based metal-ferroelectric-metal (MFM) capacitor was implemented and the polarization switching dynamics, along with the ferroelectric characteristics, of the device were analyzed. In addition, a study was conducted to propose an applicable model of HfO₂-based MFM capacitors by applying various ferroelectric switching characteristics models.

• 한국자기학회지
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• 제17권3호
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• pp.120-123
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• 2007

이 연구에서는 Ta 45/Ru 9.5/IrMn 10/CoFe $3/AlO_x$/자유층/$AlO_x$/CoFe 7/IrMn 10/Ru 60(nm) 구조를 갖는 이중장벽 자기터널접합(double-barrier magnetic tunnel junction: DMTJ)를 다루었다. 자유층은 $Ni_{16}Fe_{62}Si_8B_{14}\;7nm$, $Co_{90}Fe_{10}(fcc)$ 7 nm 및 $CoFet_1$/NiFeSiB $t_2$/CoFe $t_1$으로 구성하였으며 두께 $t_1,\;t_2$는 변화시켰다. 즉 TMR비와 RA를 개선하기 위하여 부분적으로 CoFe층을 대체할 수 있는 비정질 NiFeSiB층이 혼합된 자유층 CoFe/NiFeSiB/CoFe을 갖는 DMTJ를 연구하였다. NiFeSiB($t_1=0,\;t_2=7$)만의 자유층을 갖는 DMTJ는 터널자기저항(TMR)비 28%, 면적-저항곱(RA) $86k{\Omega}{\mu}m^2$, 보자력($H_c$) 11 Oe 및 층간 결합장($H_i$) 20 Oe를 나타내었다. $t_1=1.5,\;t_2=4$인 경우의 하이브리드 DMTJ는 TMR비 30%, RA $68k{\Omega}{\mu}m^2$ 및 $H_c\;11\;Oe$를 가졌으나 $H_i$는 37 Oe로 증가하였다. 원자현미경(AFM)과 투과전자현미경(TEM)측정을 통하여 NiFeSiB층 두께가 감소하면 $H_i$가 증가하는 것을 확인하였다. 비정질 NiFeSiB층이 두꺼워지면 보통 계면의 기복을 유도하는 원주형성장(columnar growth)를 지연시키는데 유효하였다. 그러나 NiFeSiB층이 얇으면 표면거칠기는 증가하고 전자기적 Neel 결합 때문에 Hi는 커졌다.