• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.310-310
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• 2016

최근 NAND flash memory는 높은 집적성과 데이터의 비휘발성, 낮은 소비전력, 간단한 입, 출력 등의 장점들로 인해 핸드폰, MP3, USB 등의 휴대용 저장 장치 및 노트북 시장에서 많이 이용되어 왔다. 특히, 최근에는 smart watch, wearable device등과 같은 차세대 디스플레이 소자에 대한 관심이 증가함에 따라 유연하고 투명한 메모리 소자에 대한 연구가 다양하게 진행되고 있다. 대표적인 플래시 메모리 소자의 구조로 charge trapping type flash memory (CTF)가 있다. CTF 메모리 소자는 trap layer의 trap site를 이용하여 메모리 동작을 하는 소자이다. 하지만 작은 window의 크기, trap site의 열화로 인해 메모리 특성이 나빠지는 문제점 등이 있다. 따라서 최근, trap layer에 다양한 물질을 적용하여 CTF 소자의 문제점을 해결하고자 하는 연구들이 진행되고 있다. 특히, 산화물 반도체인 zinc oxide (ZnO)를 trap layer로 하는 CTF 메모리 소자가 최근 몇몇 보고 되었다. 산화물 반도체인 ZnO는 n-type 반도체이며, shallow와 deep trap site를 동시에 가지고 있는 독특한 물질이다. 이 특성으로 인해 메모리 소자의 programming 시에는 deep trap site에 charging이 일어나고, erasing 시에는 shallow trap site에 캐리어들이 쉽게 공급되면서 deep trap site에 갇혀있던 charge가 쉽게 de-trapped 된다는 장점을 가지고 있다. 따라서, 본 실험에서는 산화물 반도체인 ZnO를 trap layer로 하는 CTF 소자의 메모리 특성을 확인하기 위해 간단한 구조인 metal-oxide capacitor (MOSCAP)구조로 제작하여 메모리 특성을 평가하였다. 먼저, RCA cleaning 처리된 n-Si bulk 기판 위에 tunnel layer인 SiO2 5 nm를 rf sputter로 증착한 후 furnace 장비를 이용하여 forming gas annealing을 $450^{\circ}C$에서 실시하였다. 그 후 ZnO를 20 nm, SiO2를 30 nm rf sputter로 증착한 후, 상부전극을 E-beam evaporator 장비를 사용하여 Al 150 nm를 증착하였다. 제작된 소자의 신뢰성 및 내구성 평가를 위해 상온에서 retention과 endurance 측정을 진행하였다. 상온에서의 endurance 측정결과 1000 cycles에서 약 19.08%의 charge loss를 보였으며, Retention 측정결과, 10년 후 약 33.57%의 charge loss를 보여 좋은 메모리 특성을 가지는 것을 확인하였다. 본 실험 결과를 바탕으로, 차세대 메모리 시장에서 trap layer 물질로 산화물 반도체를 사용하는 CTF의 연구 및 계발, 활용가치가 높을 것으로 기대된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.871-877
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• 1998

Electroluminescent(EL) devices based on organic materials have been of great interest due to their possible applications for large-area flat-panel displays, where they are attractive because of their capability of multicolor emission, and low operation voltage. In this study, glass substrate/ITO/Eu(TTA)$_3$(phen)/Al, glass substrate/ITO/Eu(TTA)$_3$(phen)/Al and glass substrate/ITO/Eu(TTA)$_3$(phen)/AlQ$_3$/Al structures were fabricated by vacuum evaporation method, where aromatic diamine(TPD) was used as a hole transporting material, Eu(TTA)$_3$(phen) as an emitting material, and Tris(8-hydroxyquinoline) aluminu-m(AlQ$_3$) as an electron transporting layer. Electrolumescent(EL) and I-V characteristics of Eu(TTA)$_3$-(-phen) were investigated. These structures show the red EL spectra, which are almost the same at the PL spectrum of Eu(TTA)$_3$(phen). I-V characteristics of this structure show that turn-on voltage was 9V and current density was 0.01A/㎤ at a operation voltage of 9V. Electrical transporting phenomena of these structures were explained using the trapped-charge-limited current model with I-V characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.97-100
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• 1992

The Degradation mechanism of the ZnO-varistor fabricated with the content of a 3-Composition seed grain is discussed using the method of Thermally Stimulated Current (TSC). The spectra of TSC is measured in the temperature range of -130～270$^{\circ}C$ with a various forming electric fields E$\sub$f/, temperature T$\sub$f/ time tf, and a various rising rate of temperature. It is observed that there are appeared the peaks of ${\alpha}$, ${\alpha}$$_2$, ${\beta}$ and ${\gamma}$from high temperature in a TSC spectrum. It seems that ${\alpha}$$_1$ peak is due to thermal depolarization of donor ions forming the space charge in the depletion layer, and ${\alpha}$$_2$peak is due to the detrapping of trapped electrons in deep trap level of intergranular layer, and ${\beta}$ peak is due to the thermal exciting of carrier existing in the donor level of grain itself, and ${\gamma}$ peak is due to the thermal exciting of trapped carrier in all shallow trap site randomly distributed in the inner of sample and/or a intrinsic impurity existing in it.

• Bulletin of the Korean Chemical Society
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• v.15 no.9
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• pp.752-758
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• 1994

Several one-electron reduction products of ${\gamma}$(1,2)-[$H_nSiV_2W_{10}O_{40}]^{(6-n)-}$ were separated by precipitating or coprecipitating with diamagnetic host compounds at different pH. Mono-and diprotonated species, 1 and 2, in powder samples exhibit aPR spectra characteristic of a mononuclear oxovanadium species, indicating that the unpaired electron is trapped at one vanadium atom. The EPR spectrum of the unprotonated species 0 shows 15 parallel lines, indicating that the unpaired electron interacts equally with two vanadium atoms. While different species were precipitated depending upon the pH of the solution and the charge of the host anion, only one species 1' was formed in the frozen solutions at pH 3.2-4.7. The EPR spectrum of 1' indicates that the unpaired electron is trapped at one vanadium atom and 1/16 of the spin density is delocalized onto the second vanadium atom. The species 1' is probably another form of the monoprotonated species. The EPR spectra show that some of 2 transform into 1 and some of 0 transform into 1' in the solid state at low temperatures. It is suggested that proton transfer between the heteropolyanion and water molecues in the solid state is involved in these transformations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1512-1519
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• 2013

Oil-impregnated paper is a major type of insulation used in oil-filled converter transformers for both traditional and new energy systems. This paper presents and analyzes the results of the experiment conducted on the electrical aging of oil-impregnated paper under AC-DC combined voltages using the pulsed electro-acoustic (PEA) technique. The formation and dynamics of space charge affected the performance of insulation material. The electrical aged oil-paper insulation was obtained through electrical aged experiments under the voltages. Based on the PEA technique, measurements were carried out when the oil-paper insulation system was subjected to different stressing and aging times. The space charge dynamics in the bulk of the oil-paper insulation system with different aging times were measured and analyzed. Characteristic parameters such as the total charge injection amount, the total charges of fast moving and slow moving, and the distortion factor of electric field were calculated and discussed. Results show that the longer electrical aging time, the more charges trapped in the bulk of aging sample. It leads to larger distortion factor of electric field in the bulk of aging samples and accelerate degradation of oil-paper insulation under AC-DC combined voltages.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.7
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• pp.615-619
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• 2008

A molecular memory device which has a structure of Al/$Al_2O_3$/ASA-15 LB monolayer/Ti/Al device, was fabricated. To study a charge transfer mechanism of molecular memory devices, current density-voltage (J-V) characteristics were measured at an increasing temperature range from 10 K to 300 K with an interval of 30 K. Strong temperature-dependent electrical property and tunneling through organic monolayer at low bias (below 0.5 V) were appeared. These experimental data were fitted by using a theoretical formula such as the Simmons model. In comparison between the theoretical and the experimental results, it was verified that the fitting results using the Simmons model about direct tunneling was fairly fitted below 0.5 V at both 300 K and 10 K. Hopping conduction was also dominant at all voltage range above 200 K due to charges trapped by defects located within the dielectric stack, including the $Al_2O_3$, organic monolayer and Ti interfaces.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.1
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• pp.112-116
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• 2007

We have investigated the hysteresis phenomenon of a hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) and analyzed the effect of hysteresis phenomenon when a-Si:H TFT is a pixel element of active matrix organic light emitting diode (AMOLED). When a-Si:H TFT is addressed to different starting gate voltages, such as 10V and 5V, the measured transfer characteristics with 1uA at $V_{DS}$ = 10V shows that the gate voltage shift of 0.15V is occurred due to the different quantities of trapped charge. When the step gate-voltage in the transfer curve is decreased from 0.5V to 0.05V, the gate-voltage shift is decreased from 0.78V to 0.39V due to the change of charge do-trapping rate. The measured OLED current in the widely used 2-TFT pixel show that a gate-voltage of TFT in the previous frame can influence OLED current in the present frame by 35% due to the change of interface trap density induced by different starting gate voltages.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.