• Journal of Multimedia Information System
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• v.8 no.2
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• pp.143-146
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• 2021

This work presents an automated transistor biasing scheme for analog integrated circuits. In order to effectively bias the transistor at a desired operating point, the proposed method uses a linearized transistor circuit model along with the curve fitted expressions obtained from the pre-simulated I-V characteristics of the actual transistor. As a result, the transistor size that leads to the desired operating point can be easily determined without heavily relying on the circuit simulator, which will lead to significant design time reduction. Furthermore, the proposed method is applied to an actual amplifier circuit where the design time based on the proposed biasing method showed 10× faster than the conventional design approach using the circuit simulator.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.653-659
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• 2008

This paper describes the design of high power transistor packages using high power chip transistor dies, chip capacitors and a new wire bonding technique. Input impedance variation and output power performances according to wire inductance and resistance for internal matching are also discussed. A multi crossing type(MCT) wire bonding technique is proposed to replace the conventional stepping stone type(SST) wire bonding technique, and eventually to improve the output power performances of high power transistor packages. Using the proposed MCT wire bonding technique, it is possible to design high power transistor packages with highly improved output power compared to SST even the package size is kept to be the same.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.75-87
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• 2012

A design paradigm using sequential geometric programming is presented to accurately design CMOS op amps with BSIM3. It is based on new adaptive modeling of transistor parameters through the operating point simulation. This has low modeling cost as well as great simplicity and high accuracy. The short-channel dc, high-frequency small-signal, and short-channel noise models are used to characterize the physical behavior of submicron devices. For low-power and low-voltage design, this paradigm is extended to op amps operating in the subthreshold region. Since the biasing and modeling errors are less than 0.25%, the characteristics of the op amps well match simulation results. In addition, small dependency of design results on initial values indicates that a designed op amp may be close to the global optimum. Finally, the design paradigm is illustrated by optimizing CMOS op amps with accurate transfer function.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.234-241
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• 2012

This paper proposes a novel design methodology considering transistor layout variation. The proposed design technique is to improve the transistor's electrical characteristics without performing a circuit simulation to extract transistor layout variation. There are three advantages in the proposed method. Firstly, there is no need to change the normal design flow used in layout designs. Secondly, there is no need to perform simulation in order to extract the transistor layout variation. Thirdly, early warnings in layout design lead to decreasing the number of post layout simulations. Less post layout simulations will decrease the number of iterations in the design cycle and shorten design period. The number of bad transistors in the early design phase were reduced from 17.8% to 2.9% by applying eDRC environment for layout designers to develop Standard Cell Library.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.2
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• pp.7-14
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• 1979

Design considerations of I2L are discussed with particular emphasis on the upward current gain of the npn transistor, 6J Several test structures have been fabricated to measure the DC and AC characteristics of the I2L basic cell and the base current components of the npn transistor. A T flip-flop has also been designed and fabricated using the I2L technology. The upward current gain of 10 the speed -power product of the 2.6pJ/gate and the minimum propagation delay time of 36 nsec have been obtained from the test structure. The maxmum toggle frequency of the T flip -flop has been measured to be 3.5 MHz.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.9
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• pp.1359-1368
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• 1989

In this paper, the composite BiCMOS transistor which combines a bipolar transistor and a MOS transistor in a cascade type, is analyzed in terms of I-V characteristics and small signal equivalent circuit. As a result, it has a larger driving capability than MOS transistor and a more extended rante of input voltage than bipolar transistor. Next, a BiCMOS differential amplifier as its application example is designed and compared with the CMOS one and the bipolar one. It increases the driving capability of the CMOS differential amp and improves the linear operation region of the bipolar differential amp.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.415-419
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• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.1943-1950
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• 2009

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.