• 제목/요약/키워드: transistor

검색결과 2,880건 처리시간 0.03초

High Temperature Electrical Behavior of 2D Multilayered MoS2

  • 이연성;정철승;백종열;김선국
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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    • pp.377-377
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    • 2014
  • We demonstrate the high temperature-dependent electrical behavior at 2D multilayer MoS2 transistor. Our previous reports explain that the extracted field-effect mobility of good device was inversely proportional to the increase of temperature. Because scattering mechanism is dominated by phonon scattering at a well-designed MoS2 transistor, having, low Schottky barrier. However, mobility at an immature our $MoS_2$ transistor (${\mu}m$ < $10cm^2V^{-1}s^{-1}$) is proportional to the increase temperature. The existence of a big Schottky barrier at $MoS_2-Ti$ junction can reduce carrier transport and lead to lower transistor conductance. At high temperature (380K), the field-effect mobility of multilayer $MoS_2$ transistor increases from 8.93 to $16.9cm^2V^{-1}sec^{-1}$, which is 2 times higher than the value at room temperature. These results demonstrate that carrier transport at an immature $MoS_2$ with a high Schottky barrier is mainly affected by thermionic emission over the energy barrier at high temperature.

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Two transistor 포워드 DC-DC 컨버터의 효율 특성에 관한 연구 (A study on the efficiency characteristics for two transistor Forward DC-DC converter)

  • 안태영;이광택
    • 전력전자학회논문지
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    • 제12권1호
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    • pp.50-55
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    • 2007
  • 본 논문에서는 Two transistor forward(TTF) DC-DC 컨버터의 회로방식에 대한 전력변환 효율특성을 빠르고 효과적인 분석 방법에 대해 보고한 것이다. TTF 컨버터의 회로 구성 소자 중에서 내부 기생저항만을 고려한 등가회로를 유도하고 이상적인 동작 파형을 이용하여 전류의 실효값과 전도손실을 유도하였다. 해석을 간단하게 하기위해서 정상상태 결과로부터 코어 손실은 무시하였으며, 다이오드의 손실과 전도손실 만을 고려하였다. 해석결과의 타당성을 검토하기 위해서 시험용 TTF 컨버터를 구성하여 검증하였다. 입력전압 390V, 출력전압 12V, 최대전력 480W의 조건에서 실험결과와 해석결과와 비교적 잘 일치한다는 것을 본 논문에서 확인 하였다.

부분분리 매립 채널 어레이 트랜지스터의 총 이온화 선량 영향에 따른 특성 해석 시뮬레이션 (Simulation of Characteristics Analysis by Total Ionizing Dose Effects in Partial Isolation Buried Channel Array Transistor)

  • 박제원;이명진
    • 전기전자학회논문지
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    • 제27권3호
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    • pp.303-307
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    • 2023
  • 본 논문은 Buried Channel Array Transistor(BCAT) 소자의 Oxide 내부에 Total Ionizing Dose(TID) effects으로 인한 Electron-Hole Pair의 생성이 유도되어, Oxide 계면의 Hole Trap Charge의 증가에 따른 누설전류의 증가와 문턱 전압의 변화를 기존에 제안한 Partial Isolation Buried Channel Array Transistor(Pi-BCAT)구조와 비교 시뮬레이션 하여, Pi-BCAT 소자의 증가한 Oxide 면적과 상관없이 변화한 누설전류와 문턱 전압에서의 특성이 비대칭 도핑 BCAT 구조보다 우수함을 보여 준다.

Impact of Gamma Irradiation Effects on IGBT and Design Parameter Considerations

  • Lho, Young-Hwan
    • ETRI Journal
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    • 제31권5호
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    • pp.604-606
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    • 2009
  • The primary dose effects on an insulated gate bipolar transistor (IGBT) irradiated with a $^{60}Co$ gamma-ray source are found in both of the components of the threshold shifting due to oxide charge trapping in the MOS and the reduction of current gain in the bipolar transistor. In this letter, the IGBT macro-model incorporating irradiation is implemented, and the electrical characteristics are analyzed by SPICE simulation and experiments. In addition, the collector current characteristics as a function of gate emitter voltage, VGE, are compared with the model considering the radiation damage of different doses under positive biases.

개선된 소프트 스위칭 Two-transistor forward converter (An Improved Soft Switching Two-transistor Forward Converter)

  • Kim, Marn-Go
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2000년도 전력전자학술대회 논문집
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    • pp.137-140
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    • 2000
  • This paper proposes an improved soft switching two-transistor forward converter which uses a novel lossless snubber circuit to effectively control the turn-off dv/dt rate of the main transistors. In the proposed soft switching implementation the turn-off voltage traces across the main two transistors are almost the same contributing to reduce the total capacitive turn-on loss and the snubber current is divided into the two transistors resulting in distributed thermal stresses

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Hot carrier에 의한 GAA MOSFET의 열화현상 (Hot Carrier Induced Device Degradation in GAA MOSFET)

  • 최락종;이병진;장성준;유종근;박종태
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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    • pp.5-8
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    • 2002
  • Hot carrier induced device degradation is observed in thin-film, gate-all-around SOI transistor under DC stress conductions. We observed the more significant device degradation in GAA device than general single gate SOI device due to the degradation of edge transistor. Therefore, it is expected that the maximum available supply voltage of GAA transistor is lower than that o( bulk MOSFET or single gale SOI device.

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Single Transistor에 의한 전파정류 Technique (A Technique for Full Wave Rectification using a Single Transistor)

  • 이주근;이동근
    • 대한전자공학회논문지
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    • 제15권3호
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    • pp.7-10
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    • 1978
  • 이 논문은 single transistor를 사용하여 정현파를 전파정류하는 한 방법을 검토한다. switching으로 동작되는 inverter에 R-feed back을 하고 최적 parameter를 설정하므로써 도통상태의 반파와 cut-off 상태에서 feed back을 통한 반파를 합성하여 전파정류의 출력을 얻는다. cassette deck의 code재생 system에 이용한 바 효과적이었고, AGC 등에 이용 가능하다.

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인공지능 기법을 이용한 CMOS 표준셀의 심볼릭 레이아웃 발생기 (A Symbolic Layout Generator for CMOS Standard Cells Using Artificial Intelligence Approach)

  • 유종근;이문기
    • 대한전자공학회논문지
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    • 제24권6호
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    • pp.1080-1086
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    • 1987
  • SLAGEN, a system for symbolic cell layout based on artificial intelligence approach, takes as input a transistor connection description of CMOS standard cells and environment information, and outputs a symbolic layout description. SLAGEN performas transistor grouping by a heuristic search method, in order to minimize the number of separations, and then performs group reordering and transistor reordering with an eye toward minimizing routing. Next, SLAGEN creates a rough initial routing in order to guarantee functionality and correctness, and then improve the initial routing by a rule-based approach.

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3- Transistor Cell OTP ROM Array Using Standard CMOS Gate-Oxide Antifuse

  • Kim, Jin-Bong;Lee, Kwy-Ro
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제3권4호
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    • pp.205-210
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    • 2003
  • A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

X-shaped Conjugated Organic Materials for High-mobility Thin Film Transistor

  • Choi, Dong-Hoon;Park, Chan-Eon
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.310-311
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    • 2009
  • New X-shaped crystalline molecules have been synthesized through various coupling reactions and their electronic properties were investigated. They exhibit good solubility in common organic solvents and good self-film forming properties. They are intrinsically crystalline as they exhibit well-defined X-ray diffraction patterns from uniform and preferred orientations of molecules. They also exhibited high field effect mobilities in thin film transistor (TFT) and good device performances.

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