• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.428-431
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• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Transactions on Electrical and Electronic Materials
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• v.4 no.6
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• pp.32-37
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• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.2
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• pp.17-24
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform new both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of 1011~1021[states/eV/cm2] after a stress voltage. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Proceedings of the IEEK Conference
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• summer
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• pp.209-212
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• 2004

In this paper, The stress induced leakage currents of thin silicon oxides is investigated in the nano scale structure implementation for Soc. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41\square\;and\;113.4\square,$ which have the channel width x length 10x1um, respectively. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• Journal of the korean Society of Automotive Engineers
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• v.15 no.3
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• pp.111-119
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• 1993

In this study, the transient impact structural stress analysis of tracked vehicle structures under recoil impact load is investigated. ANSYS, ABAQUS Code are used for modelling and analytical procedures. The highest maximum Tresca stress occurs on race ring portion and its stress level is (.sigma.$_{T}$)$_{max}$ =20-40kgf/m $m^{2}$. The second highest stress occurs on upper plate of chassis and down plate of turret. The maximum stress level increases with loading direction and elevation angle. The results from liner static load analysis are very much different with impact analysis. Therefore, the practical solutions of structures under impact load can be obtained by only nonlinear transient impact analysis. The impact stress analysis of the steel vehicle structures is conducted. The maximum stress level is less than (.sigma.$_T/)$_{max}$m $m^{2}$. So, the design concept of steel structures can be adapted for new alternatives.s.s.s..s.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1993.10a
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• pp.482-487
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• 1993

A prediction method for determining the welding residual stress by artificial neural network is proposed. A three-dimensional transient thermomechanical analysis has been performed for the CO $_{2}$ Arc Welding using the finite element method. The validity of the above results is demonstrated by experimental elastic stress relief method which is called Holl Drilling Method. The first part of numarical analysis performs a three-dimensional transient heat transfer anslysis, and the second part then uses results of the first part and performs a three-dimensional transient thermo-clasto-plastic analysis to compute transient and residual stresses in the weld. Data from the finite element method were used to train a backpropagation neural network to predict residual stress. Architecturally, the finite element method were used to train a backpropagation voltage and the current, a hidden layer to accommodate failure mechanism mapping, and an output layer for residual stress. The trained network was then applied to the prediction of residual stress in the four specimens. The results of predicted residual stress have been very encouraging.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.371-371
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• 2010

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the MEMS implementation with nano structure. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41{\AA}$, which have the gate area $10^{-3}cm^2$. The stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.102-105
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• 1997

The thickness dependence of stress voltage oxide currents has been measured in oxides with thicknesses between 10nm and 80nm. The oxide currents were shown to be composed of stress current and transient current. The stress current was caused by trap assited tunneling through the oxide. The transient current was caused by the tunneling charging and discharging of the trap in the interfaces. The stress current was used to estimate to the limitations on oxide thicknesses. The transient current was used to the data retention in memory devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.43-46
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.335-340
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• 2002

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4${\AA}$ and 814${\AA}$, which have the gate area $10^3cm^2$. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.