• Journal of electromagnetic engineering and science
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• 제8권3호
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• pp.114-118
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• 2008

Direct-conversion RF front-end for 5-GHz WLAN is implemented in $0.18-{\mu}m$ CMOS technology. The front-end consists of a low noise amplifier, and low flicker noise down-conversion mixers. For the mixer, an inductor is included to resonate out parasitic tail capacitances in the transconductance stage at the operating frequency, thereby improves the flicker noise performance of the mixer, and the overall noise performance of the front-end. The receiver RF front-end has 6.5 dB noise figure, - 13 dBm input IP3, and voltage conversion gain of 20 dB with the power consumption of 30 mW.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.359-363
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• 2011

To integrate the sensor driver and logic circuits, fabricating down scaled transistors has been main issue. At this research, short channel effects were analyzed after n channel polycrystalline silicon thin film transistor was fabricated at high temperature. As a result, on current, on/off current ratio and transconductance were increased but threshold voltage, electron mobility and s-slope were reduced with a decrease of channel length. When carriers that develop at grain boundary in activated polycrystalline silicon have no gate biased, on current was increased with punch through by drain current. Also, due to BJT effect (parallel bipolar effect) that developed under region of channel by increase of gate voltage on current was rapidly increased.

• Transactions on Electrical and Electronic Materials
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• 제14권6호
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• pp.291-294
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• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1998년도 학술발표대회 논문집 제17권 2호
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• pp.177-180
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• 1998

높은 Q가 요구되는 고주파 신호 처리용 필터 설계에서는 흔히 SC 필터를 사용하고 있다. 처리하고자 하는 신호가 고주파수이고, 선택도 Q 값이 매우 높은 경우에는, SC 필터에 사용하는 증폭기의 성능이 빠르고, 직류 성분 이득이 커야만 한다. 이와 같은 속도와 이득이 요구됨에 따라 일반적인 범용 증폭기는 이득이 충분치 못하여 사용이 제한되고, 설사 범용 증폭기를 이용하여 필터를 구성하였다 해도 그 특성에 많은 제한을 줄 수밖에 없다. 또한 GaAS MESFET op amp의 경우, 최근의 논문에서도 60[dB] 이상의 이득이 제안된 바 없으므로, 필터 구성시 또 다른 설계 기술이 요구된다. 따라서 본 논문에서는 GaAS MESFET 능동 SC 적분기의 유한한 이득과 offset 전압을 보정한 새로운 구조의 적분기를 제안한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.7-8
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• 2006

The effects of heat treatment on the electrical properties of SGOI were examined. We proposed the optimized heat treatments for improving the interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA(rapid thermal annealing) before gate oxidation and post-RTA after dopant activation, the driving current, the transconductance, and the leakage current were improved significantly.

• ETRI Journal
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• 제31권3호
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• pp.342-344
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• 2009

From a hydrodynamic device simulation for the pseudomorphic high electron mobility transistors (pHEMTs), we observe an increase of maximum extrinsic transconductance and a decrease of source-drain capacitances. This gives rise to an enhancement of the switching speed and isolation characteristics as the upper-to-lower planar-doping ratios (UTLPDR) increase. On the basis of simulation results, we fabricate single-pole-double-throw transmitter/receiver monolithic microwave integrated circuit (MMIC) switches with the pHEMTs of two different UTLPDRs (4:1 and 1:2). The MMIC switch with a 4:1 UTLPDR shows about 2.9 dB higher isolation and approximately 2.5 times faster switching speed than those with a 1:2 UTLPDR.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1706-1711
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• 1989

Unit processes for the fabrication of HEMT(high electron mobility transistor)was studied and the optimum conditions of them were applied to the fabrifcation of a discrete HEMT device. The HEMT with a nominal gate-source spacing of 3.6\ulcorner and a gate length of 2.8\ulcorner showed a transconductance of 46.1mS/mm and a threshold voltage of -0.29V. A source-drain voltage of 2.0V for a saturation current of 35mA/mm was achieved.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.351-354
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• 1998

In this paper, electrical characteristics of an n-channel Si MOSFET with L$_{s}$=0.6.mu.m under optical illumination are charaterized on wafer. Energetic photons with .gamma.=830nm, hv=1.494eV, P$_{opt}$=300mW are injected near the drain junction, the most photoresponsive region in the device, via optical fiber. We observed significantly increased drain current and transconductance, which is considered to be useful for the implementation of OEICs on silicon substrate, under optical control with P$_{opt}$=300mW. Optical power-dependent physical mechanisms responsible for the variation of electrical characteristics under optical input are also reported.d.d.d.

• 전자공학회논문지A
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• 제30A권2호
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• pp.36-45
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• 1993

The n-channel MOSFETs with gate-$n^{-}$S/D overlapped structure have been fabricated by ITLDD(inverse-T gate lightly doped drain) technology. The gate length(L$_{mask}$) was 0.8$\mu$m. The degradation effects of hot carriers injected into the gate oxide were analyzed in terms of threshold voltage, transconductance and drain current variations. The degradation dependences on the gate voltage and drain voltage were characterized. The devices with higher n-concentration showed higher resistivity against the hot carrier injection. As the results of investigating the lifetime of the device, the lifetime showed longer than 10 years at V$_{d}$ = 5V for the overlapped devices with the implantation of an phosphorus dose of 5$\times$10$^{13}$ cm$^{-2}$ and an energy of 80 keV in the n$^{-}$resion.

• 전자공학회논문지A
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• 제30A권8호
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• pp.49-56
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• 1993

In this paper, we present a new lifetime prediction model for PMOSFET by using the correlation between transconductance degradation and substrate current influence. The suggested model is applied to a different channel structured PMOSFET, dgm/gm of both SC-PMOSFET and BC-PMOSFET appear with one straigth line about Qbib, therefore, this model is independent of channel structure. The suggested model is applied to a different drain structured SC-PMOSFET. Unlike S/D structured SC-PMOSFET, dgm/gm of LDD structured SC-PMOSFET appears with one straight line about Qb, therefore, this model is dependent of drain structure.