• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.12
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• pp.1315-1320
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• 2015

In this paper Communication data link equipment on a high speed-hopping method to use the frequency resources efficiently for the frequency environment is introduced such as sensing techniques, using the same frequency band by using the received two-channel technique and the receive filter bank unit applied to be shared with other equipment such as radar and so on. The real-time measurement and analysis were operated for measurement the frequency environment of the operating band in advance. and primarily equipment to develop is analyzed how the interference effect to the radar minimize the operation of radar equipment. In reverse, to use the same frequency band the methods such as frequency sharing techniques are presented in this paper. Finally, by design of the main items of the RF transceiver NF, transmission output, and a simulation of the IMD, such as whether the key is verified prior to meet specifications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.38-44
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• 2008

In this paper, we introduce an low complexity and low power IR-UWB (impulse radio ultra wideband) baseband transceiver for wireless sensor network. The proposed baseband, implemented by TSMC 0.18um CMOS technology, has a simple structure in which a simplified packet structure and a digital synchronizer with 1-bit sampler to detect incoming pulses are used. Besides, clock gating method using gated clock cell as well as customized clock domain division can reduce the total power consumption drastically. As a result, the proposed baseband has about 23K digital gates with an internal memory of 2Kbytes and achieves about 1.8mW@1Mbps power consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1038-1044
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• 2011

In this paper, the multichannel intermediate frequency transceiver for broadband multimedia system is designed and the experimental results are analyzed. Basic elements of the transceiver such as frequency synthesizer, amplifier, mixer, automatic gain control amplifier are introduced. The analysis technique described here applies not only to amplifier but also to any other nonlinear components such as mixers and frequency doubler. Through the investigation of the power spectrum density of the transmitted signal, the phase noise of the local oscillator is evaluated below 70 dBc/kHz. The frequency characteristics of the modulated signal is flat within the system bandwidth. Also the effects of adjacent channel interference and supurious emission are analyzed. And the function of automatic gain control amplifier is well operated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.668-670
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• 2017

Visible Light Communication, which is promising as a next generation near field wireless communications, has been increased study and application case due to the development of LED technology. However, there are few application cases to IoT service due to the necessity of separate equipment for communication and limitation of light transmission to obstacles. In this paper, it propose a portable VLC transceiver module that can be connected to USB OTG and dedicated application for control to realization position possible necessary technique. The string input from the dedicated application is sent to the VLC module via USB OTG to transmit and receive data between the modules. As string transmission experiment result, it is confirmed that ASCII code transmission between VLC transceiver modules is possible through control of the implemented dedicated application.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.36-44
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• 2016

In this paper, an Impulse Radio-Ultra Wide band RF Transceiver for WBAN applications is implemented in $0.18{\mu}m$ CMOS technology. The designed RF transceiver support 3-5GHz UWB low band and employs OOK(On-Off Keying) modulation. The receiver employs non-coherent energy detection architecture to reduce complexity and power consumption. For the rejection of the undesired interferers and improvement of the receiver sensitivity, RF active notch filter is integrated. The VCO based transmitter employs the switch mechanism. As adapt the switch mechanism, power consumption and VCO leakage can be reduced. Also, the spectrum mask is always same at each center frequency. The measured sensitivity of the receiver is -84.1 dBm at 3.5 GHz with 1.579 Mbps. The power consumption of the transmitter and receiver are 0.3nJ/bit and 41 mW respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1658-1664
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• 2007

The popularity of OFDM systems is being increased because of high speed data transmission capability md the spectral efficiency characteristics. However, since OFDM systems are very sensitive to the Doppler spread, The interference among subcarriers and the total system noise can be increased seriously due to the degree of Doppler effects which can cause the orthogonality problems. Therefore, these Doppler effects were analyzed using the Doppler spectrum models by varying its parameters. Especially in this paper, The degree of system performance degradation was investigated for the OFDM systems applying the relatively simple transmit and receiver diversity. The degree of the system performance degradation depends on the specific diversity structures of transceiver systems. Here, the performances of OFDM systems with two antennas transceiver diversity were analyzed and compared with that of systems with only transmission diversity and without diversity as the Doppler characteristics varied.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.5
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• pp.2357-2380
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• 2019

In this paper, we investigate the impact of hardware impairments (HWIs) on the performance of a downlink massive MIMO system. We consider a single-cell system with maximum ratio transmission (MRT) as precoding scheme, and with all the HWIs characteristics such as phase noise, distortion noise, and amplified thermal noise. Based on the system model, we derive closed-form expressions for a typical user data rate under two scenarios: when a common local oscillator (CLO) is used at the base station and when separated oscillators (SLOs) are used. We also derive closed-form expressions for the downlink transmit power required for some desired per-user data rate under each scenario. Compared to the conventional system with ideal transceiver hardware, our results show that impairments of hardware make a finite upper limit on the user's downlink channel capacity; and as the number of base station antennas grows large, it is only the hardware impairments at the users that mainly limit the capacity. Our results also show that SLOs configuration provides higher data rate than CLO at the price of higher power consumption. An approach to minimize the effect of the hardware impairments on the system performance is also proposed in the paper. In our approach, we show that by reducing the cell size, the effect of accumulated phase noise during channel estimation time is minimized and hence the user capacity is increased, and the downlink transmit power is decreased.

• Journal of IKEEE
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• v.26 no.4
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• pp.659-670
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• 2022

An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS signal has a phase shifted by 90° compared to the DQ signals. In the receive operation, the read time calibration is performed by per-pin skew calibration and clock-domain crossing within a byte. The implemented transceiver for the LPDDR2 memory controller is designed by using a 55-nm process using a 1.2V supply voltage and has a maximum signal transmission rate of 830 Mb/s/pin. The area and power consumption of each lane are 0.664 mm² and 22.3 mW, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.2B
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• pp.130-137
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• 2012

In this paper, we propose core and edge router architectures with LPI(Low Power Idle) for reducing energy consumption in OBS networks. The proposed core router architecture is comprised of a BCP switch, a burst switch, line cards and sleep/wake controller for LPI. When the offered load of network is low, sleep/wake controller can change the state of the core router line card from active to sleep state for saving the energy after receiving network control packet. The edge router consists of a switch for access line card, a SCU and OBS edge router line cards. The LPI function in edge router line card is performed through network level control by network control packet, individually. Additionally, PHY/transceiver modules can transition active state to sleep state when burst assemble engine generates new bursts. To evaluate the energy saving performance of proposed architecture with LPI, the power consumption of each router is analyzed by using data sheet of commercial router and optical device. And, simulation is also performed in terms of sleep time of PHY/Transceiver through OPNET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.