• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• Journal of Electrical Engineering and Technology
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• 제4권1호
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• pp.118-122
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• 2009

Organic thin film transistors with a pentacene active layer and various polymer gate insulators were fabricated and their performances were investigated. Characteristics of pentacene thin film transistors on different polymer substrates were investigated using an atomic force microscope (AFM) and x-ray diffraction (XRD). The pentacene thin films were deposited by thermal evaporation on the gate insulators of various polymers. Hexamethyldisilazane (HMDS), polyvinyl acetate (PVA) and polymethyl methacrylate (PMMA) were fabricated as the gate insulator where a pentacene layer was deposited at 40, 55, 70, 85, 100 oC. Pentacene thin films on PMMA showed the largest grain size and least trap concentration. In addition, pentacene TFTs of top-contact geometry are compared with PMMA and $SiO_2$ as gate insulators, respectively. We also fabricated pentacene TFT with Poly (3, 4-ethylenedioxythiophene)-Polysturene Sulfonate (PEDOT:PSS) electrode by inkjet printing method. The physical and electrical characteristics of each gate insulator were tested and analyzed by AFM and I-V measurement. It was found that the performance of TFT was mainly determined by morphology of pentacene rather than the physical or chemical structure of the polymer gate insulator

• Journal of Information Display
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• 제7권1호
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• pp.1-6
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• 2006

A 10" carbon nanotube field emission display device was fabricated with a novel structure with a hopping electron spacer (HES) by screen printing technique. HES plays a role of preventing the broadening of electron beams emitted from carbon nanotubes without electrical discharge during operation. The structure of the novel tetrode is composed of carbon nanotube emitters on a cathode electrode, a gate electrode, an extracting electrode coated on the top side of a HES, and an anode. HES contains funnel-shaped holes of which the inner surfaces are coated with MgO. Electrons extracted through the gate are collected inside the funnel-shaped holes. They hop along the hole surface to the top extracting electrode. In this study the effects of the addition of HES on emission characteristics of field emission display were investigated. An active ozone treatment for the complete removal of residues of organic binders in the emitter devices was applied to the field emission display panel as a post-treatment.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 춘계학술대회논문집A
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• pp.741-744
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• 2000

In general there occur warpage in one way long part. Warpage is caused by differential shrinkage-Orientation Effect, Volumetric Shrinkage Effect, Differential Cooling Effect -over the part. Deco-Top is located at the top of 29"TV set and it's shape is one way long$(626{\times}130mm)$. Material is used transparency ABS resin. So we can't design ribs in this part. And we use film gate to avoid weld line. In these reasons we must develop no ribs and no warpage product. In this study we use MOLDFLOW's software-MF/FLOW, MF/COOL, MF/WARP. Using MF/FLOW, set the flow balance and gate positioning. And we can set cooling channel layout and the optimum processing condition through MF/COOL and MF/WARP. In result we reduced trials and obtained good product.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.907-909
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• 2009

Low voltage operated top gated polymer transistors were fabricated with a high permittivity polymer, P(VDF-TrFE) and F8T2 as a gate dielectric and semiconducting layer, respectively. The operating voltage of transistors was effectively reduced under -10 V and typical threshold voltages were as low as -1 ~ -4 V with the reasonable charge carrier mobility of $10^{-3}cm^2$/Vs for the amorphous polymer. The large hysteresis in transfer curve was improved effectively by annealing at low temperature.

• 한국정보통신학회논문지
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• 제19권1호
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• pp.163-168
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• 2015

본 연구에서는 10 nm이하 채널길이를 갖는 비대칭 이중게이트 MOSFET의 하단 게이트 전압에 대한 터널링 전류(tunneling current)의 변화에 대하여 분석하고자한다. 단채널 효과를 감소시키기 위하여 개발된 다중게이트 MOSFET중에 비대칭 이중게이트 MOSFET는 채널전류를 제어할 수 있는 요소가 대칭형의 경우보다 증가하는 장점을 지니고 있다. 그러나 10nm 이하 채널길이를 갖는 비대칭 이중게이트 MOSFET의 경우, 터널링 전류에 의한 차단전류의 증가는 필연적이다. 본 연구에서는 차단전류 중에 터널링 전류의 비율을 계산함으로써 단채널에서 발생하는 터널링 전류의 영향을 관찰하고자 한다. 포아송방정식을 이용하여 구한 해석학적 전위분포와 WKB(Wentzel-Kramers-Brillouin) 근사를 이용하여 터널링 전류를 구하였다. 결과적으로 10 nm이하의 채널길이를 갖는 비대칭 이중게이트 MOSFET에서는 하단 게이트 전압에 의하여 터널링 전류가 크게 변화하는 것을 알 수 있었다. 특히 채널길이, 상하단 산화막 두께 그리고 채널두께 등에 따라 매우 큰 변화를 보이고 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.6-6
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• 2009

We present an alternative process whereby deuterium is delivered to the location where the gate oxide reside by an implantation process. Deuterium ions were implanted using different energies to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas was performed to remove the D-implantation damage. We have observed that deuterium ion implantation into the gate oxide region can successfully remove the interface states and the bulk defects.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1270-1272
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• 2007

Analytic equations are derived from physical quantities in the gate-source overlap region and the concept of effective gate-source overlap length is proposed. The effective overlap length can be affected by gate voltage, insulator thickness and semiconductor thickness, and the overlap length should be larger than the length to obtain maximum driving current.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.108-110
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• 2018

This paper proposes shortcircuit fault protection method in a synchronous buck converter using the PCB pattern Rogowski coil. The PCB pattern Rogowski coils are embedded in the gate driver to measure the device currents of the top and bottom side. When shortcircuit occurs in the system, the gate signal is blocked by the proposed fault protection method using the device current. The simulation and experimental results show that the proposed fault protection method is verified in the shortcircuit system.

• 천문학회보
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• 제37권1호
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• pp.93.2-93.2
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• 2012

Point Spread Function (PSF) is one of the most important optical characteristics for describing the performance of a telescope. And a concept of subpixelization is inevitable in evaluating the undersampled PSF (Shin and Sakurai 2009). Then, the internal structure of Yohkoh SXT CCD pixel is not uniform: For the top half of pixel area, the X-ray should pass a so-called gate structure where the charges are transferred to an output amplifier. This gate structure shows energy-dependent sensitivity (Tsuneta et al. 1991). For example, for Al-K (8.34 A) X-ray emission, the transmission of the polysilicon gate is about 0.9. Also, for the peak coronal response of the SXT thin filters, around 17 angstrom (0.729 keV), the transmission of the gate is about 0.6, falling off sharply towards longer wavelengths. It should be noted that this spectrally dependent non-uniform response of each CCD pixel will certainly have a noticeable effect on the properties of the PSF at longer wavelengths. Therefore, especially for analyzing the undersampled PSF of low energy source, a careful consideration of non-uniform internal pixel structure is required in determining the shape of the PSF core. The details on the effect of gate structure will be introduced in our presentation.