• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.7
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• pp.1617-1622
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• 2015

This paper analyzes the ratio of tunneling current for channel doping concentration of sub-10 nm asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current in subthreshold region increases in the region of channel length of 10 nm below. Even though asymmetric DGMOSFET is developed to reduce short channel effects, the increase of tunneling current in sub-10 nm is inevitable. As the ratio of tunneling current in off current according to channel doping concentration is calculated in this study, the influence of tunneling current to occur in short channel is investigated. To obtain off current to consist of thermionic emission and tunneling current, the analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for channel doping concentration in sub-10 nm asymmetric DGMOSFET, specially with parameters of channel length, channel thickness, and top/bottom gate oxide thickness and voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1465-1470
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• 2017

In conventional MOSFETs, the silicon thickness is always larger than inversion layer, so that the drain induced barrier lowering (DIBL) is expressed as a function of oxide thickness and channel length regardless of silicon thickness. However, since the silicon thickness is fully depleted in the sub-10 nm low doped double gate (DG) MOSFET, the conventional SPICE model for DIBL is no longer available. Therefore, we propose a novel DIBL SPICE model for DGMOSFETs. In order to analyze this, a thermionic emission and the tunneling current was obtained by the potential and WKB approximation. As a result, it was found that the DIBL was proportional to the sum of the top and bottom oxide thicknesses and the square of the silicon thickness, and inversely proportional to the third power of the channel length. Particularly, static feedback coefficient of SPICE parameter can be used between 1 and 2 as a reasonable parameter.

• ETRI Journal
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• v.27 no.5
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• pp.525-532
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• 2005

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

• Journal of information and communication convergence engineering
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• v.14 no.1
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• pp.40-44
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• 2016

The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T_ILD and dielectric constant ε_r of the inter-layer distance (ILD), the doping concentration N_d (N_a), and length L_g of the channel, and the side-wall length L_SW where the stacked FETs are coupled are studied. When N_d (N_a) < 10¹⁶ cm^-3 and L_SW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N_d (N_a) > 10¹⁶ cm^-3 or L_SW > 20 nm, the shift decreases and increases, respectively. M3INVs with T_ILD ≥ 50 nm and ε_r ≤ 3.9 can neglect the interaction between the stacked FETs, but when T_ILD or ε_r do not meet the above conditions, the interaction must be taken into consideration.

• Korean Journal of Heritage: History & Science
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• v.51 no.3
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• pp.72-87
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• 2018

This study highlights a drainage gate and a ditch, which existed around the whole area of the western shore of Wolji Pond(月池) and focuses on a possible connection between the drainage facility on the western shore and the historical drainage system of Wolji Pond. Specifically, it primarily considered locations and the form of a drainage gate, the relationship between northwestern ditch of Wolji Pond and the drainage gate, and the establishment period and the character of the drainage facility on the western shore. The drainage gate found in excavation in 1975 is determined as the same facility as Surakgu(水落口) recorded on an actual measurement drawing, 1922. Therefore, it is highly probable that there were already the drainage facility in the western shore of Wolji Pond before the 1920s. The drainage gate constructed by processing rectangular stones has four drainage holes for controlling water level. The way of the drainage through the drainage holes is the same as that of the northern shore of Wolji Pond. From a cadastral map drawn in 1913, it is found that the ditch existed in northwest of Wolji Pond. The ditch was proximate to the drainage gate and shared the same axes. Hence, the ditch and the drainage gate are determined as a organic facility connected to the drainage system of Wolji Pond. In particular, the ditch existed in northwest of Wolji Pond is the basis for judging that the drainage facility in the western shore were established before the 1910s. Water flowed in through drainage holes of the drainage gate is drained into the northwest of Wolji Pond, through the ditch. The establishment period and the intention of the drainage facility on the western shore can be interpreted in two aspects. First, they might be 'a agricultural irrigation facility in the Joseon era', given that Wolji Pond was recorded as a agricultural reservoir, and that the whole northwestern area of Wolji Pond was used as farm land areas. Second, they might be 'a drainage facility for controlling the water level in creating Wolji Pond', given that the drainage gate was annexed to the lower shore forming the waterline of Wolji Pond, and that the hight of drainage holes on top of the drainage gate was similar to the full water level of Wolji Pond. Considering the related grounds and circumstance, the latter possibility is high.

• Journal of Korea Water Resources Association
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• v.31 no.4
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• pp.397-406
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• 1998

The Pyokkolche Reservoir was constructed as a major public project of the ancient agricultural society, 1600 years ago. From a hydraulic point of view, it is considered to have been carried out with a distinguished technology. It should be in particular noticed that for a consecutive banking the main stream was diverted and drained to the Yonpo stream and the dam with same sea levels on its top along the whole length was built in a nearly straight line in spite of the different sea levels between both ends on the bottom. These suggest that the carrying out artifice and surveying technigue of those days were considerably excellent. However, the insufficient plan and design at the time of the construction, the temporary management and the repeated repair works in the later ages caused the Pyokkolche to lose its function. The Changsaenggeo and Kyungjanggeo gate sites being the facilities for sluices composed of a simple span and a vertical lift hand-operated sing a pully. The advantage of the geographical characteristics at both ends of the main dam was scientifically taken to these sites which also functioned as a spillway against a flood. The gate site of Suyogeo must have been located in an entrance to Suwolri, the northern end of the Pyokkolche and Yutonggeo is presumed to have been located on the right of Sangsori, the southern end of the Pyokklche. Keywords : Pyokkolche Reservoir, construction technology, gate site location.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1342_1342
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• 2009

Zinc tin oxide (ZTO) based thin-film transistors (TFTs) were fabricated on glass substrate by using sol-gel method. The fabricated ZTO TFT had bottom gate and top contact structure with ZTO layer formed by spin coating from ZTO solution. The fabricated TFT showed field-effect mobility of about 2 - $4\;cm^2/V{\cdot}s$ with on/off current ratios >$10^7$, and threshold voltage of 2 V.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1249-1252
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• 2007

We have fabricated 3.5” transparent AM-OLED panel driven by PEALD grown ZnO TFT. The performance of ZnO thin film transistor was improved by adapting top gate structure, protection layer for ZnO from photolithography process, optimizing temperature and plasma power of ZnO growth process. The ZnO-TFT has a mobility of $8.9cm^2/V.s$, a subthreshold swing of 0.95V, and an on/off ratio of $10^7$.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.113-116
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• 2008

The active layer thickness and curing condition dependent performance of an organic thin film transistor (OTFT) with inkjetted organic semiconductor (OSC) layer is studied The best performance of the OTFT was found when the thickness of ose was ~120 nm cured at $60^{\circ}C$. The performance enhancement of the OTFT with inkjetted OSC layer was discussed by comparing the OTFT with spin-coated ose layer.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1568-1570
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• 2008

In this paper, fabrication of a $60{\times}48$ polymer TFT array with a top-gate structure on plastic substrates using a low temperature printing process will be presented and the device structure and manufacturing processes will be discussed. The polymer TFT array showed excellent air stability and uniform electrical characteristics over a large area. Finally, a 1.5 inch EPD display with 50 dpi resolution using the polymer TFT array will be demonstrated for e-film device applications.