• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7C
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• pp.644-651
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• 2007

In multiple antenna systems, vertical Bell Labs Layered Space-Time (V-BLAST) systems enable very high throughput by nulling and cancelling at each layer detection. In this paper, we propose a V-BLAST system which combines with signal space diversity technique. The benefit of the signal space diversity is that we can obtain an additional gain without extra bandwidth and power expansion by applying inphase/quadrature interleaving and the constellation rotation. Through simulation results, it is shown that the performance of the proposed system is less than 0.5dB away from the ideal upper bound.

• Journal of Communications and Networks
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• v.6 no.1
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• pp.1-8
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• 2004

In this paper, we investigate the properties and performance of space-time bit-interleaved coded modulation (STBICM) systems in fast Rayleigh fading channels. We first show that ST-BICM with QPSK signaling in fast fading channels possesses the uniform distance property, which makes performance analysis tractable. We also derive the probability distribution of the squared Euclidean distance between space-time symbols assuming uniform bit-interleaving. Based on the distribution, we show that the diversity order for each codeword pair becomes maximized as the frame length becomes sufficiently long. This maximum diversity order property implies that the bit-interleaver transforms an ST-BICM system over transmit diversity channels into an equivalent coded BPSK system over independent fading channels. We analyze the performance of ST-BICM in fast fading channels by deriving an FER upper bound. The derived bound turns out very accurate, requiring only the distance spectrum of the binary channel codes of ST-BICM. Numerical results demonstrate that the bound is tight enough to render an accurate estimate of performance of ST-BICM systems.

• ETRI Journal
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• v.31 no.6
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• pp.795-802
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• 2009

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT-DMB) baseband receiver SoC. The AT-DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T-DMB system; therefore, a conventional T-DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT-DMB baseband receiver SoC is fabricated using 0.13 ${\mu}m$ technology and shows successful operation with a 50 mW power dissipation.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.715-718
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• 1998

본 논문에서는 시분할 구조와 1.5bit 디지털 에러보상을 사용하여 작은 면적을 갖는 저 전압, 저전력 10bit 1㎒ 사이클릭 A/D 변환기를 제안하였다. 제안된 사이클릭 A/D 변환기는 시분할 구조를 사용함으로서 변환속도의 향상과 저 전력 특성을 가질 수 있었으며 1.5bit 디지털 에러 보상을 사용함으로서 10bit의 고해상도와 저 전력 특성을 구현할 수 있었다. 제안된 사이클릭 A/D 변환기는 0.6㎛ CMOS Nwell 공정 parameter로 simulation 하였으며 layout 결과 칩면적은 1.1㎜×0.8㎜ 이며 이는 비슷한 성능을 갖는 다른 A/D 변환기에 비하여 매우 작은 크기이다. 제안된 사이클릭 A/D 변환기는 3V의 전원전압에 1.6㎽의 전력소모를 갖는다. Matlab simulation 결과 INL, DNL은 각각 0.6LSB, 0.7LSB 이하의 값을 보였다.

• Proceedings of the KSMRM Conference
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• 2001.11a
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• pp.113-113
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• 2001

Purpose： In the gradient echo EPI the conventional T2＊-weighted image is poor in signal as well distorted by the field inhomogeneity. By acquiring a proton density image in addition to th T2＊-weighted image at the same scan, the fMRI processing can be improved. Method： The central region of the k space is acquired twice at different time points after th RF pulse while acquiring the other regions onc as described in Fig. 1. In Fig. 1 the segment numbers are chronological. Then, we can get two images of different contrast by interleaving th central region in the k space as done in the dua contrast FSE.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.309-315
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• 1998

This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for Integrated Services Digital Network (ISDN) applications. The proposed ADC based on the improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADCs to increase throughput rate. Moreover, the ADC employs the interpolation technique in the back-end subranging ADCs far residue signal processing to minimize die area and power consumption. The fabricated and measured prototype ADC in a 0.8 um n-well double-poly double-metal CMOS process typically shows a 52 MHz sampling rate at a 5 V supply voltage with 230 mW, and a 40 MHz sampling rate at a 3 V power supply with 60 mW power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3C
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• pp.311-321
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• 2009

This paper proposes an efficient frequency offset estimation algorithm for MB-OFDM based UWB systems. The time-frequency interleaving in MB-OFDM extends the time-interval between two transmitted OFDM symbols in the same sub-band. The extended time-interval causes not only the degradation of the system performance by reducing frequency offset estimation range, but also the increase of the hardware complexity by requiring the larger number of storing samples. The proposed estimation algorithm expands the estimation range by applying the proposed sign detection scheme. Simulation results show that the estimation range is increased above 30 ppm compared with a conventional auto-correlation based scheme. The estimation is performed on only one sub-band, and the frequency offsets of the others are calculated by relation to center frequency. This way reduced the number of the storing samples by about l/3. The frequency offset estimator with the proposed algorithm was designed into the architecture which minimizes hardware overhead by time-sharing operators and memory units, and which was synthesized to gate-level circuits using $0.13{\mu}m$ CMOS technology, and the total gates were about 47K.

• The KIPS Transactions:PartB
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• v.10B no.2
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• pp.143-150
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• 2003

Error concealment plays an important role in combating transmission errors. Methods of error concealment which produce better quality are generally of higher complexity, thus making some of the more sophisticated algorithms is not suitable for real-time applications. In this paper, we develop temporal and spatial error resilient video encoding and data hiding approach to facilitate the error concealment at the decoder. Block interleaving scheme is introduced to isolate erroneous blocks caused by packet losses for spatial area of error resilience. For temporal area of error resilience, data hiding is applied to the transmission of parity bits to protect motion vectors. To do error concealment quickly, a set of edge features extracted from a block is embedded imperceptibly using data hiding into the host media and transmitted to decoder. If some part of the media data is damaged during transmission, the embedded features are used for concealment of lost data at decoder. This method decreases a complexity of error concealment by reducing the estimation process of lost data from neighbor blocks. The proposed data hiding method of parity bits and block features is not influence much to the complexity of standard encoder. Experimental results show that proposed method conceals properly and effectively burst errors occurred on transmission channel like Internet.

• ETRI Journal
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• v.27 no.5
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• pp.525-532
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• 2005

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.25-31
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• 2013

In this paper, a new interleaving method for spatially-multiplexed multi-input-multi-output (SM-MIMO) scheme in an integrated mobile satellite and terrestrial system is proposed. In the proposed scheme, the transmitted bits for satellite path are interleaved in an innovative way to make sure that bits multiplied with different channel gains will be located alternatively in one received codeword after demapping, in order to compensate the performance degradation due to high-correlation of the satellite path. In addition, the interleaver can be implemented in a computationally efficient way and with the minimum time delay.