• Title/Summary/Keyword: time sequential simulation

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A Simulation Study on the Overhaul Repair Shop of Weapon System (전면정비방식의 무기체계 정비공장에 대한 시뮬레이션 연구)

  • Shin, Kyeong-Wook;Lee, Geun-Hyu;Moon, Dug-Hee
    • Journal of the Korea Society for Simulation
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    • v.20 no.3
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    • pp.119-127
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    • 2011
  • Overhaul and repair service means the sequential processes of disassembly, repair and reassembly for a product which has been used for a long time. Overhaul is required for the companies producing airplanes, ships, trains, military weapons and heavy industrial equipments which are very expensive and have a long life cycle. The most important performance measure of the overhaul repair shop is usually the lead time. Thus, how to design the manufacturing system to meet the delivery date is a major concern in overhaul repair shop. This paper introduces the case study of an overhaul repair shop producing military weapon systems with the 3D simulation tool, $QUEST^{TM}$. At first, the characteristics of overhaul shop and what should be considered for simulation modeling are explained. Then, various simulation scenarios including two types of disassembly systems, one is flow line system and the other is cell system, are discussed with the results of simulation experiments.

Developing a New Risk Assessment Methodology for Distribution System Operators Regulated by Quality Regulation Considering Reclosing Time

  • Saboorideilami, S.;Abdi, Hamdi
    • Journal of Electrical Engineering and Technology
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    • v.9 no.4
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    • pp.1154-1162
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    • 2014
  • In the restructured electricity market, Performance-Based Regulation (PBR) regime has been introduced to the distribution network. To ensure the network stability, this regime is used along with quality regulations. Quality regulation impose new financial risks on distribution system operators (DSOs). The poor quality of the network will result in reduced revenues for DSOs. The mentioned financial risks depend on the quality indices of the system. Based on annual variation of these indices, the cost of quality regulation will also vary. In this paper with regard to reclosing fault in distribution network, we develop a risk-based method to assess the financial risks caused by quality regulation for DSOs. Furthermore, in order to take the stochastic behavior of the distribution network and quality indices variations into account, time-sequential Monte Carlo simulation method is used. Using the proposed risk method, the effect of taking reclosing time into account will be examined on system quality indicators and the cost of quality regulation in Swedish rural reliability test system (SRRTS). The results show that taking reclosing fault into consideration, affects the system quality indicators, particularly annual average interruption frequency index of the system (SAIFI). Moreover taking reclosing fault into consideration also affects the quality regulations cost. Therefore, considering reclosing time provides a more realistic viewpoint about the financial risks arising from quality regulation for DSOs.

Design and Implementation of Client-Server Model on Virtual Real-time Interactive Distributed Simulation Environment Using Web (웹을 이용한 가상 실시간 상호작용 분산 시뮬레이션 환경엣 클라이언트-서버 모델의 설계 및 구현)

  • Jeong, Jin-Rip;U, Yeong-Je;Jeong, Chang-Seong
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.1
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    • pp.57-65
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    • 1999
  • The simulation which is larger scale, complex and interactive with clients treat a lot of messages. It can be thinking more efficient distributed simulation than sequential one. The training simulation with multi-users is geographically distributed, and required high cost to operate and maintain system as increasing user requirements. The adaptation of web technology to the simulation can be a way to solves it without cost added. But dynamic web environment can causes causality error of events. This paper is concerned with client-server model, which supports interaction between distributed simulation server and web browser, and it is implemented by Java distributed object model. the result have shown that the distributed simulation is performed correctly on dynamic environment.

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Comparison of Prediction Algorithms in Tracking System of Multiple Vehicles (다중차량 추적시스템의 예측 알고리듬 비교)

  • Kim, In-Haeng;Kim, Whoi-Yul
    • Journal of Advanced Navigation Technology
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    • v.3 no.2
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    • pp.156-166
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    • 1999
  • In multi-vehicle tracking systems Kalman filter is generally used for tracking vehicles. Despite well known advantages of Kalman filter that presents optimality with constraints, it is difficult to track several vehicles in real time simultaneously due to a large number of computations. In this paper, we propose a multi-vehicle tracking system with an adaptive predictor that employs recursive least square algorithm which can be easily implemented for real time application on a transversal filter. The performance of the proposed tracking system is compared to one with Kalman filter using a synthetic sequential image generated by computer graphics and real sequential image taken at intersections. Simulation results show that the proposed tracking system can be applied to track vehicles in real sequential image at the rate of 30 frame/sec on a PC environments without any special hardwares.

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A Study of Delay Test for Sequential circuit based on Boundary Scan Architecure (순서회로를 위한 경계면 스캔 구조에서의 지연시험 연구)

  • Lee, Chang-Hee;Kim, Jeong-Hwan;Yun, Tae-Jin;Nam, In-Gil;Ahn, Gwang-Seon
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.3
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    • pp.862-872
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    • 1998
  • In this paper, we developed a delay test architecture and test procedure for clocked sequential circuit. In addition, we analyze the problems of conventional and previous method on delay test for clocked sequential circuit in IEEE 1149.1. This paper discusses several problems of Delay test on IEEE 1149.1 for clocked sequential circuit. Previous method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a method called ARCH-S, is based on a clock counting technique to generate continuous clocks for clocked input of CUT. A 4-bit counter is selected for the circuit under test. The simulation results ascertain the aecurate operation and effectiveness of the proposed architecture.

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An Efficient Hybrid Diagnosis Algorithm for Sequential Circuits (순차 회로를 위한 효율적인 혼합 고장 진단 알고리듬)

  • 김지혜;이주환;강성호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.5
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    • pp.51-60
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    • 2004
  • Due to the improvements in circuit design and manufacturing technique, the complexity of a circuit is growing. Since the complexity of a circuit causes high frequency of faults, it is very important to locate faults for improvement of yield and reduction of production cost. But unfortunately it takes a long time to find sites of defects by e-beam proving if the physical level. A fault diagnosis algorithm in the Sate level has meaning to reduce diagnosis time by limiting fault sites. In this paper, we propose an efficient fault diagnosis algorithm in the logical level. Our method is hybrid fault diagnosis algorithm using a new fault dictionary and additional fault simulation which minimizes memory consumption and simulation time.

A Pattern Comparison Algorithm for Pruning Fault Candidates (고장 대상 후보를 줄이기 위한 패턴 비교 알고리즘)

  • Cho, Hyung-Jun;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.82-88
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    • 2007
  • In this paper, we present a pattern comparison algorithm for reducing fault candidate lists. The number of fault candidates determines the total fault simulation time. To decrease the total fault diagnosis time, the reduction of the number of fault candidates is essential. Critical path tracing determines fault candidate lists detected by a set of tests using a backtracing algorithm starting at the primary outputs of a circuit. The proposed algorithm reduces fault candidates comparing failing patterns with good patterns during critical path tracing process. As we reduce all fault candidates of the circuit to more accurately suspected fault candidates, we can greatly reduce fault simulation time. The proposed algorithm greatly increases simulation speed than that of a conventional backtracing method. The proposed algorithm is applicable to both combinational and sequential circuits. Experimental results on ISCAS#85 and ISCAS#89 benchmark circuits showed fault candidates are pruned and fault diagnosis time is also decreased in proportion to fault candidate decrease.

Asymptotic properties of monitoring procedure for parameter change in heteroscedastic time series models (이분산 시계열 모형에서 모수의 변화에 대한 모니터링 절차의 점근 성질)

  • Kim, Soo Taek;Oh, Hae June
    • The Korean Journal of Applied Statistics
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    • v.33 no.4
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    • pp.467-482
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    • 2020
  • We investigate a monitoring procedure for the early detection of parameter changes in location-scale time series models. We introduce a detector for monitoring procedure based on modified residual cumulative sum (CUSUM). The asymptotic properties of the monitoring procedure are established under the null and alternative hypotheses. Simulation results and data analysis are also provided for illustration.

Effective Algorithm for the Low-Power Set-Associative Cache Memory (저전력 집합연관 캐시를 위한 효과적인 알고리즘)

  • Jung, Bo-Sung;Lee, Jung-Hoon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.9 no.1
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    • pp.25-32
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    • 2014
  • In this paper, we proposed a partial-way set associative cache memory with an effective memory access time and low energy consumption. In the proposed set-associative cache memory, it is allowed to access only a 2-ways among 4-way at a time. Choosing ways to be accessed is made dynamically via the least significant two bits of the tag. The chosen 2 ways are sequentially accessed by the way selection bits that indicate the most recently referred way. Therefore, each entry in the way has an additional bit, that is, the way selection bit. In addition, instead of the 4-way LRU or FIFO algorithm, we can utilize a simple 2-way replacement policy. Simulation results show that the energy*delay product can be reduced by about 78%, 14%, 39%, and 15% compared with a 4-way set associative cache, a sequential-way cache, a way-tracking cache, and a way cache respectively.

The Effect of Multiple Energy Detector on Evidence Theory Based Cooperative Spectrum Sensing Scheme for Cognitive Radio Networks

  • Khan, Muhammad Sajjad;Koo, Insoo
    • Journal of Information Processing Systems
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    • v.12 no.2
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    • pp.295-309
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    • 2016
  • Spectrum sensing is an essential function that enables cognitive radio technology to explore spectral holes and resourcefully access them without any harmful interference to the licenses user. Spectrum sensing done by a single node is highly affected by fading and shadowing. Thus, to overcome this, cooperative spectrum sensing was introduced. Currently, the advancements in multiple antennas have given a new dimension to cognitive radio research. In this paper, we propose a multiple energy detector for cooperative spectrum sensing schemes based on the evidence theory. Also, we propose a reporting mechanism for multiple energy detectors. With our proposed system, we show that a multiple energy detector using a cooperative spectrum sensing scheme based on evidence theory increases the reliability of the system, which ultimately increases the spectrum sensing and reduces the reporting time. Also in simulation results, we show the probability of error for the proposed system. Our simulation results show that our proposed system outperforms the conventional energy detector system.