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An Efficient Hybrid Diagnosis Algorithm for Sequential Circuits  

김지혜 (삼성전자 반도체 총괄 시스템 LSI 사업부)
이주환 (연세대학교 전기전자공학)
강성호 (연세대학교 전기전자공학부)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.5, 2004 , pp. 51-60 More about this Journal
Abstract
Due to the improvements in circuit design and manufacturing technique, the complexity of a circuit is growing. Since the complexity of a circuit causes high frequency of faults, it is very important to locate faults for improvement of yield and reduction of production cost. But unfortunately it takes a long time to find sites of defects by e-beam proving if the physical level. A fault diagnosis algorithm in the Sate level has meaning to reduce diagnosis time by limiting fault sites. In this paper, we propose an efficient fault diagnosis algorithm in the logical level. Our method is hybrid fault diagnosis algorithm using a new fault dictionary and additional fault simulation which minimizes memory consumption and simulation time.
Keywords
순차회로;고장 진단;고장 딕셔너리;고장 시뮬레이션;
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  • Reference
1 P. G. Ryan and W. K. Fuchs, 'Dynamic Fault Dictionaries and Two-Stage Fault Isolation,' Transactions on IEEE VLSI System, pp. 176-180, 1998   DOI   ScienceOn
2 B. Chess and T. Larrabeee, 'Creating Small Fault Dictionaries,' Transactions on IEEE Computers-Aided Design, pp. 346-356, 1999   DOI   ScienceOn
3 V. Boppana, I.Hartanto and W. K. Fuchs, 'Full Fault Dictionary Storage Based on Labeled Tree Encoding,' Transactions on IEEE Computers-Aided Design, pp. 255-268, 1998
4 I. Pomeranz and S. M. Reddy, 'On the Generation of Small Dictionaries for Fault Location.' Proc. of IEEE Intl. Conf. on Computer Aided Design, pp. 272-279, 1992   DOI
5 H. Lee, D. Ha, ' Hope: An Efficient Parallel Fault Simulator,' Proc. of Design Automation Conference, pp 336-340, 1992   DOI
6 I. Pomeranz, S. M. Reddy, ' Fault Diagnosis Based on Parameters of Output Responses,' Proc. of Pacific Rim International Symposium, pp. 139-147, 2000   DOI
7 V, Boppana and W. K. Fuchs 'Fault Dictionary compaction by Output Sequence Removal,' Proc. of IEEE ACM Intl. Conf. pp. 576-579, 1994
8 K. Shigeta, T. Ishiyama, 'An Improved Fault Diagnosis Algorithm Based on Path Tracing with Dynamic Circuit Extraction,' Proc. of IEEE International Test Conference, pp. 235-244, 2000   DOI
9 K. Shigata, T. Ishiyama, A Nnew Path Tracing Algorithm with Dynamic Circuit Extraction for Sequential Circuit Fault Diagnosis,' Proc. of VLSI Test Symposium, pp. 48-53, 1998   DOI
10 A. W. John and L. Eric, 'Failure Diagnosis of Structured VLSI,' Proc. of IEEE Design & Test of Computers, pp. 49 - 60, 1989   DOI   ScienceOn
11 I. Pomeranz and S.M. Reddy, 'On Dictionary-Based Fault Location in Digital Logic Circuits,' Transactions on IEEE Computers, pp. 48-59, 1997   DOI   ScienceOn
12 S. Venkataraman, I. Hartanto, W. Kent Fuchs, 'Dynamic Diagnosis of Sequential Circuits Based on Stuck-at Faults,' Proc. of VLSI Test Symposium, pp. 198-203, 1996   DOI
13 D. B. Lavo and Tracy Larrabee, 'Making Cause-Effect Cost Effective : Low-Resolution Fault Dictionaries,' Proc. of IEEE Intl Test Conf, pp. 278-286, 2001   DOI