• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.682-684
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• 2004

The effect of 1/f noise by the random telegraph signal(RTS) on the phase noise and the jitter of CMOS ring Oscillator is investigated. 10 parallel piece-wise-linear current sources connected to each node model the RTS signals. The In, the power spectral density and the jitter of output of the ring oscillator are simulated as functions of the amplitude and time constant of RTS current source. It is confirmed that the increase of amplitude of RTS is directly related to the increase of the width of phase noise md the value of jitter. The shorter the time constant is, the wider width of FET peak and the larger value of cycle to cycle jitter are.

• Journal of IKEEE
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• v.25 no.2
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• pp.234-242
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• 2021

In case implementation of microwave photonic (MWP) systems for phased array radars (PARs), noise and time delay error should be minimized to obtain accurate beam direction. Time delay error in MWP systems is generated from signal noise and timing jitter. In this paper, noise and timing jitter in MWP systems for PAR is researched, also according to the amplification of an erbium-doped fiber amplifier, noise and timing jitter variation is verified by an experiment. Timing jitter is decreased and SNR is increased if we amplify the signal by using an erbium-doped fiber amplifier, up to the amplification rate of signal and noise is similar.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.722-737
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• 2011

In this paper, we propose an estimation of network jitter that occurs when transmitting TCP packets containing MPEG-2 TS in progressive streaming service over wired or wireless Internet networks. Based on the estimated network jitter size, we can calculate required de-jitter buffering time to absorb the network jitter at the receiver side. For this purpose, by exploiting the PCR timestamp existing in the TS packet header, we create a new timestamp information that is marked in the optional field of TCP packet header to estimate the network jitter. By using the proposed de-jitter buffering scheme, it is possible to employ the conventional T-STD buffer model without any modification in the progressive streaming service over IP networks. The proposed method can be applicable to the recently developed international standard, MPEG DASH (dynamic adaptive streaming over HTTP) technology.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.4
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• pp.93-99
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• 2011

This paper proposes a novel network jitter estimation algorithm for robust VoIP communication system. The proposed method computes the current network environment mode using the differences of arrival time and generation time from sequential received packets. According to the current network environment mode, the jitter variance weights is adjusted to minimize the error for estimating the network jitter. The jitter average and variance are calculated by the autoregressive estimated algorithm, and then the network jitter is estimated by applying the jitter variance weights.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.1
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• pp.11-16
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• 2010

This paper compares and studies scheduling methods to reduce jitter in real-time control systems. While previous research has focused on dynamic-priority scheduling schemes, this paper focuses on fixed-priority scheduling which is more widely used. It is pointed out that previously defined jitter measures might not be useful in enhancing the control performance of a real-time task because the measures are relative values. We present a new jitter measure and a new scheduling scheme for fixed-priority tasks. The experimental results through simulation show that the new scheduling scheme reduces jitter and enhances control performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• ETRI Journal
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• v.33 no.3
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• pp.326-334
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• 2011

This paper outlines the time jitter effect of a sampling clock on a software-defined radio technology-based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high-speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal-to-noise ratio (SNR) characteristics of a digital IF transceiver with an under-sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency-division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.197-199
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• The Journal of the Acoustical Society of Korea
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• v.16 no.2E
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• pp.47-54
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• 1997

This paper presents two results on intersymbol interferences in baseband digital communication over an additive white Gaussian noise channel-the interferences due to mismatched square-root raised-cosine filters, in which the filters have different roll-off factors, and / or due to sampling-time jitter. The result for the mismatched filters is that even the jitter-free sampling causes intersymbol interference and it is negligibly small for a wide range of signal-to-noise ratio up to 10dB, for the roll-off factor ranging from 0.2 to 0.5, the mismatch loss being within 0.1dB from the optimum at around 10-6 .For jitter interference an approximation formula for the bit error probability is derived in case of the matched filters, which shows how the roll-off factors and the amount of jitter affect the system performance. The formula is reasonably accurate.