• Journal of Korean Society of Coastal and Ocean Engineers
• /
• v.21 no.2
• /
• pp.108-116
• /
• 2009

The present study introduces a Legendre interpolation function which is capable of analyzing wave transformation effectively in a finite element method. A Lagrangian interpolation function has been mostly used for a finite element method with a higher-order interpolation function. Although this function has an advantage of giving an accurate result with less number of elements, simulation time increases. Calculation time can be reduced by mass lumping, whereas the accuracy of solution is lowered. In this study, we introduce a modified Lagrangian interpolation function, Legendre cardinal interpolation, which can reduce simulation time with keeping up favorable accuracy. Through various numerical simulations using a Boussinesq equations model, the superiority of the Legendre cardinal interpolation function to a Lagrangian interpolation function was shown.

• Journal of IKEEE
• /
• v.19 no.1
• /
• pp.1-9
• /
• 2015

This paper proposes the design of sub-pixel interpolation circuit for real-time multi-decoder supporting 4K-UHD video images. The proposed sub-pixel interpolation circuit supports H.264, MPEG-4, VC-1 and new video compression standard HEVC. The common part of the interpolation algorithm used in each video compression standard is shared to reduce the circuit size. An intermediate buffer is effectively used to reduce the circuit size and optimize the performance. The proposed sub-pixel interpolation circuit was synthesised by using 130nm standard cell library. The synthesized gate-level circuit consists of 122,564 gates and processes 35~86 image frames per second for 4K-UHD video at the maximum operation frequency of 200MHz. Therefore, the proposed circuit can process 4K-UHD video in real time.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.4
• /
• pp.395-404
• /
• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• 제어로봇시스템학회:학술대회논문집
• /
• 2004.08a
• /
• pp.1847-1852
• /
• 2004

This article provides the connection between feedback stabilization and interpolation conditions for n-D linear systems (n > 1). In addition to internal stability, if one demands performance as a design goal, then there results an n-D matrix Nevanlinna-Pick interpolation problem. Application of recent work on Nevanlinna-Pick interpolation on the polydisk yields a solution of the problem for the 2-D case. The same analysis applies in the n-D case (n > 2), but leads to solutions which are contractive in a norm (the "Schur-Agler norm") somewhat stronger than the $H^{\infty}$ norm. This is an analogous version of the connection between the standard $H^{\infty}$ control problem and an interpolation problem of Nevanlinna-Pick type in the classical 1-D linear time-invariant systems.

• Journal of the Korean Society for Precision Engineering
• /
• v.17 no.12
• /
• pp.115-120
• /
• 2000

Increasing demands on precision machining of free-form surface have necessitated that the tool to move not only position error as small as possible, but also with smoothly varying feedrates. This paper presents new algorithm for high precision 3D(3-dimensional) NURBS(Non-Uniform Rational B-Spline) interpolation in the reference-pulse technique. Based o the minimum path error strategy, interpolation algorithm was designed to follow the NURBS curve. Using this algorithm a real-time 3D NURBS interpolator was developed in software. The algorithm implemented in a PC showed promising results in interpolation error and speed performance. It is expected that this can be applied to the CNC systems for the high precision machining of complex shapes.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.45 no.4
• /
• pp.78-83
• /
• 2008

Interpolation filters are widely used in symbol timing recovery systems to interpolate new sample values at arbitrary points between the existing discrete-time samples. Polynomial interpolation is interpolated by coefficient made inputted information. This paper presents an efficient way to implement polynomial base interpolation filters using support filter changing input. By an example, it is shown that the proposed structure out performs the conventional interpolation structure with less hardware cost.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
• /
• v.35 no.2
• /
• pp.81-90
• /
• 2017

This study aimed to construct an integrated database using the same spatio-temporal unit by employing various public-data types with different real-time information provision cycles and spatial units. Towards this end, three temporal interpolation methods (piecewise constant interpolation, linear interpolation, nonlinear interpolation) and a spatial matching method by district boundaries was proposed. The case study revealed that the linear interpolation is an excellent method, and the spatial matching method also showed good results. It is hoped that various prediction models and data analysis methods will be developed in the future using different types of data in the analysis database.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.63 no.5
• /
• pp.690-695
• /
• 2014

This paper presents a modified CCI image interpolation method based on the even-odd decomposition (EOD). The CCI method is a well-known technique to interpolate images. Although the method provides better image quality than the linear interpolation, its complexity still is a problem. To remedy the problem, this paper introduces analysis on the EOD decomposition of CCI and then proposes a reduced CCI interpolation in terms of complexity, providing better image quality in terms of PSNR. To evaluate the proposed method, we conduct experiments and complexity comparison. The results indicate that our method do not only outperforms the existing methods by up to 43% in terms of MSE but also requires low-complexity with 37% less computing time than the CCI method.

• Journal of the Korean Society for Precision Engineering
• /
• v.17 no.1
• /
• pp.192-197
• /
• 2000

In CNC machining, a free curve is cut into small linear segments using the linear interpolation(G01) method. Therefore, the interpolation error along the curve is not constant due to the changing curvature. This paper presents a NURBS (Non-Uniform Rational B-Spline) interpolation algorithm for machining free curves with high precision and high speed. The proposed NURBS interpolation defines the tool path with NURBS parameters and limits the interpolation error to any desired level by adjusting the feed rate considering the curvature of the shape and sampling time. Both linear and NURBS interpolations are compared to show the validity of the proposed algorithm.

• Proceedings of the KIEE Conference
• /
• 2007.11c
• /
• pp.83-87
• /
• 2007

Correlation Propagation Neural Networks is proposed for On-line interpolation. The proposed neural network technique is the real time computation method through the inter-node diffusion. In the network, a node corresponds to a state in the quantized input space. Each node is composed of a processing unit and fixed weights from its neighbor nodes as well as its input terminal. Information propagates among neighbor nodes laterally and inter-node interpolation is achieved. Through several simulation experiments, real time reconstruction of the nonlinear image information is processed. 1-D CPNN hardware has been implemented with general purpose analog ICs to test the interpolation capability of the proposed neural networks. Experiments with static and dynamic signals have been done upon the CPNN hardware.