• Journal of Environmental Science International
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• v.27 no.8
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• pp.723-735
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• 2018

In this study, to investigate an optimal configuration method for the modeling system, we performed an optimization experiment by controlling the types of compilers and libraries, and the number of CPU cores because it was important to provide reliable model data very quickly for the national air quality forecast. We were made up the optimization experiment of twelve according to compilers (PGI and Intel), MPIs (mvapich-2.0, mvapich-2.2, and mpich-3.2) and NetCDF (NetCDF-3.6.3 and NetCDF-4.1.3) and performed wall clock time measurement for the WRF and CMAQ models based on the built computing resources. In the result of the experiment according to the compiler and library type, the performance of the WRF (30 min 30 s) and CMAQ (47 min 22 s) was best when the combination of Intel complier, mavapich-2.0, and NetCDF-3.6.3 was applied. Additionally, in a result of optimization by the number of CPU cores, the WRF model was best performed with 140 cores (five calculation servers), and the CMAQ model with 120 cores (five calculation servers). While the WRF model demonstrated obvious differences depending on the number of CPU cores rather than the types of compilers and libraries, CMAQ model demonstrated the biggest differences on the combination of compilers and libraries.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.4
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• pp.304-310
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• 2017

In this paper, we propose the architecture of an IPM based lane detector for autonomous vehicles to detect and control the driving route along the curved lane. In the IPM image, we divide the area into two fields, Far/Near Field, and the lane candidate region is detected using the Hough transform to perform the matching for the curved lane. In autonomous vehicles, various algorithms must be embedded in the system. To reduce the system resources, we proposed a method to minimize the number of memory accesses to the image and various parameters on the external memory. The proposed circuit has 96% lane recognition rate and occupies 16% LUT, 5.9% FF and 29% BRAM in Xilinx XC7Z020. It processes Full-HD image at a rate of 42 fps at a 100 MHz operating clock.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• Journal of Broadcast Engineering
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• v.21 no.6
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• pp.944-956
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• 2016

In this paper, we propose a new hardware architecture to generate computer-generated holograms based on the block based calculation method and implement a VLSI (very large scaled integrated circuit) in ASIC (application specific integrated circuit) environment. The proposed hardware has a structure that can produce a part of a hologram in the unit of a block in parallel. After calculating a block of a hologram by using an object point, the calculation is repeated to all object points and intermediate results from them are accumulated to produce a final block of a hologram. Through this structure, we can make various size of holograms with the optimized memory access in real-time operation. The proposed hardware was implemented in the Hynix 0.18um CMOS technology of Magna chip Inc. and has 876,608 gate counts. It can generate complex holograms unlike the previous researches and stably operate in the clock frequency of 200MHz.

• Horticultural Science & Technology
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• v.29 no.6
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• pp.568-574
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• 2011

Measuring tray as a component in irrigation control system using drainage electrodes was designed and applied for tomato perlite bed culture, and the effectiveness of the irrigation control system was investigated in terms of cultural development and cultivation costs. Five different types of measuring trays equipped with drainage electrodes were tested and the traditional tray was used as the control equipped with time clock. After the first experiment, "Tube-2" was removed because of instability of water content in the substrate. After second experiment, "Tube-1" was removed because of instability of water content in the substrate and low plant yields. In third experiment, "Up-Board" exhibited the best stability in water contents and yields as well as efficiencies in water and fertilizer utilization. The "Up-Board" was the most economical and the easiest system among the tested trays. Therefore, the "Up-Board" system was concluded as the excellent design to apply for the control method using drainage electrodes for tomato perlite bed culture.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.4
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• pp.43-52
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• 2004

In this paper, the performance of the KOMPSAT-1 orbit determination (OD) accuracy at the ground station was analyzed by using the flight data. The Bayesian least squares estimation was used for the orbit determination and the assessment of the orbit accuracy was evaluated based on orbit overlap comparisons. We also compared the result from OD using GPS navigation solutions with NORAD TLE and the result from OD using range data. Furthermore, the effect of observation type and OBT drift on the accuracy was investigated. As a consequence, It is shown that the OD accuracy using only GPS position data is on the order of 5m RMS (Root Mean Square) with 4 hrs arc overlap for the 30hr arc and the GPS velocity data is not proper as a observation for the OD due to its inferior quality. The significant deterioration of the accuracy due to the critical clock bias was not founded by means of the comparison of OD result from other observations.

• Cartoon and Animation Studies
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• s.44
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• pp.285-306
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• 2016

With the increase use of smartphones, users can consume contents such as webtoon, webnovel and TV drama directly provided by the producers. In this Direct-to-Consumer era, webdrama services from the portal websites are increasing rapidly. Webdramas such as , , and can be analyzed in real time using responses such as unique users, likes, and comments. The analyses used in this research were Social Media Big Data Mining Method and Opinion Mining Method. Specific key words from webdrama can be extracted and viewers positive, neutral or negative emotion can be predicted from the words. The analyses of popular webdramas showed that the established K-Pop Idol member appearance and servicing portal site greatly influence the views, traffics, comments, and likes. Also, 'Mobile TV' proved the effectiveness as another platform other than television. Mobile targeted contents and robust business models still to be developed and identified. Overcoming these few tasks, Korea will be proven to be a webdrama content powerhouse.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• The Journal of the Korea Contents Association
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• v.14 no.3
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• pp.385-392
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• 2014

Workshift is a method of organization of working time in which workers succeed one another at the workplace. The shift work system enables round-the-clock activities required for meeting technological needs and productive and economic demands. This study tries to find the practical implications by investigating the workshift systems which are successfully applied in two representative Korean companies, Yuhan-Kimberly and POSCO. Case study method is applied in oder to analyze the special feature of shift work systems in two companies. It is concluded that the shift system(2-4system) has positively enhanced firm's capability including workers' satisfaction and commitment, product quality, and productivity. Specifically, the shiftwork system applied in the companies has significantly influenced on the workers' work-life balance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.40-47
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• 2006

The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.