• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.365-368
• /
• 2001

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• 설비공학논문집
• /
• 제17권5호
• /
• pp.404-409
• /
• 2005

This study is to investigate effects of thermal conditions on sleep. Five female university students participated in the sleep experiment. Three temperature levels (22, 26, and $30^{\circ}C$) were given, and relative humidity was maintained to $50\%$. When as subject arrived in the chamber at 9 o'clock in the evening, questionnaire was given to check physical and psychological conditions. After checking conditions, subjects went to bed till 07 : 30 in the morning. Body movement was checked during sleeping. After sleep in the chamber, questionnaire was given to the subject in order to check sleep quality. Subjects evaluated sleep quality by themselves by answering the time they fall asleep and wake up, frequency of wake during sleep, causes of each waking, and feeling after sleep. Sleep quality was rated with 7-point scale. At $30^{\circ}C$ condition, body movement was significantly higher than of other thermal conditions. The best sleep quality was obtained at the $26^{\circ}C$ condition, while the worst sleep was taken at the $30^{\circ}C$ condition.

• 한국식생활문화학회지
• /
• 제10권3호
• /
• pp.147-154
• /
• 1995

This study was conducted for the purpose of practice of nutrition education and dietary intake for college students. This survey was carried out through a variety of questionnaires by the subjects which consist of 249 male and 208 female college students in Seoul area. The results obtained were summarized as follows; 1. 75% of the subjects lived in their own houses; the monthly personal expenses were $110{\sim}200$ thousand wons. The appetite of the students who answered was normal in general. The pattern of dietary life shows that they take richer food at dinner than lunch and breakfast. 2. At school, 75% of students ate at the school cafeteria. Among several main dishes, rice was the most favorite food. Most of the subjects ate their lunch between 12 and 1 o'clock, and they spend approximately 11 to 15 minutes. Most of the students did not have lunch on time. The students ate lunch irregularly, because of the class schedule and poor appetite. 3. On weekends and vacations, 56% of the students ate lunch prepared by their mother at home. The two main reasons for skipping lunch during weekends and vacations were late breakfast and poor appetite. The frequency of eating out were $3{\sim}4$ times per week, because of social life and convenience of meal. 4. The majority of college students asked for the improvement of meal quality and the choice of menu in school cafeteria.

• 대한교통학회지
• /
• 제9권1호
• /
• pp.29-46
• /
• 1991

The purpose of this study is to develop a parking behavior model in prior step for solv-ing parking problems in Pusan C. B. D. The results of this study are as follows; In the C. B. D of Pusan the peak parking time is between 2 and 3 o'clock P. M., and the average parking duration is 237 minutes. It means the use of parking lots is very ineffi-cient. Hence in order to shorten the parking duration, it is very urgent for drivers to chan-ge parking attitude. The walking distance from the parking lots to his destination is below 300∼500m, so the establishment of parking areas and the arrangement of parking lots in C. B. D should be planned on the base of the above walking distance. The model distinguishing between legal and illegal parking behaviors is derived from the binary decision model. The selected model has the correlation rate, η2=0.505 which is relatively high value This result shows that the detetminating judgement on the legal and illegal parking behavior is influenced mutually such factors as driver's occupation parking purpose monthly income distance to his destination averaged parking duration and age.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제15권2호
• /
• pp.155-167
• /
• 2015

An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a $0.13{\mu}m$ process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.

• 한국전자파학회논문지
• /
• 제12권5호
• /
• pp.777-786
• /
• 2001

본 논문에서는 64-QAM 디지털 무선 전송장치에 적용할 목적으로 주파수 선택적 페이딩 대책 중의 하나인 디지털 기울기 등화기의 원리, 채널 모델링 및 디지털 구현방법을 분석하였다. 또한 복소 13-탭 시간영역의 적응 등화기 칩과 연동시의 성능분석을 수치계산으로 수행하였으며, 장치의 signature 특성을 통과대역 가장자리에서 약 4.5 dB 개선시킬 수 있음을 보였다. 그리고 디지털 기울기 등화기의 모델링에 대한 한계, 동작 자파수, 제어계수, 신호의 constellation, 장치의 성능에 대한 다양한 결과도 검토하였다. 끝으로 61 MHz 클럭까지 동작시험을 검증한 디지털 기울기 등화기의 칩에 대한 기능을 소개한다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.267-269
• /
• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• 방송공학회논문지
• /
• 제18권5호
• /
• pp.669-679
• /
• 2013

본 논문에서는 실시간으로 스테레오 정합을 수행하기 위한 VLSI(Very Large Scale Integrated Circuit)구조를 제안한다. 스테레오 정합의 연산을 분석하여 중간 연산 결과를 재사용하여 연산량과 메모리 접근수를 최소화한다. 이러한 동작을 수행할 수 있는 스테레오 정합 연산 셀의 구조를 제안하고, 이를 병렬적으로 확장하여 탐색 범위 내의 모든 비용함수를 동시에 연산할 수 있는 하드웨어의 구조를 제안한다. 이러한 하드웨어 구조를 확장하여 2차원 영역에 대한 비용함수를 연산할 수 있는 하드웨어의 구조와 동작을 제안한다. 구현한 하드웨어는 FPGA(Field Programmable Gate Array) 환경에서 최소 250Mhz의 클록 주파수에서 동작이 가능하고, 64화소의 탐색범위를 적용한 경우에 $640{\times}480$ 스테레오 영상을 약 805fps의 성능으로 처리할 수 있다.

• 한국통신학회논문지
• /
• 제34권1B호
• /
• pp.47-55
• /
• 2009

최근의 네트워크 침입탐지 시스템에서는 침입이 의심되는 패킷을 나타내는 데 정규표현식이 사용되고 있다. 고속 네트워크를 통해서 입력되는 패킷을 실시간으로 검사하기 위해서는 하드웨어 기반 패턴 매칭이 필수적이며 변화되는 패턴 규칙을 다루기 위해서는 FPGA와 같은 재구성 가능한 디바이스를 사용하는 것이 바람직하다. FPGA의 동작 속도 제한으로 바이트 단위의 패킷 검사로는 실시간 검사를 할 수 없는 경우에 이를 해결하기 위해서 여러 바이트 단위로 검사하는 것이 필요하다. 본 논문에서는 정규표현식 패턴 매칭을 n바이트 단위로 처리하는 하드웨어의 구조와 설계 방법을 제시하고 이에 대한 패턴 매칭 회로 생성기를 구현한다. Snort 규칙에 대해 FPGA로 합성된 하드웨어는 n=4일 때에 규칙에 따라서 $2.62{\sim}3.4$배의 처리 속도 향상을 보였다.

• 한국통신학회논문지
• /
• 제33권11C호
• /
• pp.892-897
• /
• 2008

본 논문에서는 GF$(2^m)$ 상에서 기존의 비트직렬 곱셈기에 비해 짧은 지연 시간을 갖는 새로운 디지트병렬/비트직렬 곱셈기를 제안한다. 제안된 곱셈기는 유한체 GF$(2^m)$의 다항식기저 상에서 동작하며, D 클럭 사이클마다 곱셈의 결과를 출력한다. 여기에서 D는 디지트의 크기이다. 제안된 곱셈기는 기존의 비트직렬 곱셈기 보다는 짧은 지연시간에 곱셈의 결과를 얻을 수 있고, 비트병렬 곱셈기보다는 적은 하드웨어로 구현할 수 있다. 따라서 회로의 복잡도와 지연시간 사이에 적절한 절충을 꾀할 수 있는 장점을 가지고 있다.