• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• Proceedings of the IEEK Conference
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• summer
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• pp.77-81
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• 2004

In this paper, we propose a analog front-end (AFE) for noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection. The proposed AFE are designed using 0.18 micron CMOS technology and verified by simulation using SPICE. The proposed AFE consist of Sample-and-Hold block, Analog-to-Digital converter, synchronizer, delayed clock generator and impulse generator. The time resolution of 1ns is obtained with 100MHz system clocks and the synchronized 10-bit digital outputs are delivered to the baseband. The impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results show the feasibility of the proposed UWB AFE systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.2
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• pp.151-155
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• 2008

KHST(Korean High Speed Train) has been utilized the total measurement system which evaluates the efficiency and a breakdown of the vehicle and it's results effect to secure reliability of the vehicle. Generally KHST has been received pulse signals from the wheel. It calculates the travel distance after counter the signals to confirm location information of the vehicle. However, there is a limit to measure the location of the vehicle due to slip, slide and the wheel attrition. We have developed a new measurement system by using GPS to complement those errors. In general, GPS receivers are composed of an antenna, tuned to the frequencies transmitted by the satellites, receiver-processors, and a highly-stable clock The GPS mounted on the roof of TT4 in KHST receives a signal from the RS232 communication port. It is connected to the network system in TT3 after converting with TCPIP communication. It is able to track the position of vehicle and synchronize the signal from different measurement system simultaneously. Therefore it is able to chase the fault occurrence, track inspection and electrical interruption at real-time situation more accurately. There is not an error coursed by vehicle conditions such as slip and the slide.

• Journal of Yeungnam Medical Science
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• v.2 no.1
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• pp.77-80
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• 1985

The R-R interval analyzer was developed to measure the autonomic nervous system function using microcomputer. The system based on 8 bit microcomputer including bandpass filter, R-wave detector and clock generator in order to obtain the mean value, standard deviation, total time, CV value, maximum value and minimum value in the specific view point of R-R interval variation. The pattern of R-R interval change after resting, voluntary standing and deep breathing can be analysed in normal subjects and diabetics with autonomic nervous dysfunction. The amplitude of the R-R interval variation showed sensitive pattern for normal subjects at resting, standing and deep breathing. On the contrary, the periodicities of amplitude for abnormal subjects with autonomic nervous dysfunction showed dull pattern. It was suggested that R-R interval analyzer is a good detection method for dysfunction of autonomic nervous system.

• ETRI Journal
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• v.32 no.4
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• pp.493-502
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• 2010

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.4
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• pp.314-321
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• 2005

In this paper an intelligence embedding quadruped pet robot is described. It has 15 degrees of freedom and consists of various sensors such as CMOS image, voice recognition and sound localization, inclinometer, thermistor, real-time clock, tactile touch, PIR and IR to allows owners to interact with pet robot according to human's intention as well as the original features of pet animals. The architecture is flexible and adopts various embedded processors for handling sensors to provide modular structure. The pet robot is also used for additional purpose such like security, gaming visual tracking, and research platform. It is possible to generate various actions and behaviors and to download voice or music files to maintain a close relation of users. With cost-effective sensor, the pet robot is able to find its recharge station and recharge itself when its battery runs low. To facilitate programming of the robot, we support several development environments. Therefore, the developed system is a low-cost programmable entertainment robot platform.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1527-1535
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• 1995

This paper introduces an isolated word recognition system realized on a neurocomputer called E-MIND II, which is a 2-D torus wavefront array processor consisting of 256 DNP IIs. The DNP II is an all digital VLSI unit processor for the EMIND II featuring the emulation capability of more than thousands of neurons, the 40 MHz clock speed, and the on-chip learning. Built by these PEs in 2-D toroidal mesh architecture, the E- MIND II can be accelerated over 2 Gcps computation speed. In this light, the advantages of the E-MIND II in its capability of computing speed, scalability, computer interface, and learning are especially suitable for real time application such as speech recognition. We show how to map a TDNN structure on this array and how to code the learning and recognition algorithms for a user independent isolated word recognition. Through hardware simulation, we show that recognition rate of this system is about 97% for 30 command words for a robot control.

• Sleep Medicine and Psychophysiology
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• v.5 no.1
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• pp.1-11
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• 1998

Chronobiology is the area of medicine that is, how time-related event shape our daily biologic responses and apply to any aspect of medicine with regard to altering pathophysiology and treatment response. In mammals, there are several evidences that prove suprachiasmatic nuclei(SCN) is the major circadian pacemaker and the circadian rhythm influences so many biological aspects of an living organism such as rest-activity, thermoregulation, reproduction, and endocrine system. In case of human beings, there had been little information of circadian system. That may be due to the experimental, technical difficulties to study but also to the fact that human has the more complex environments that may alter the circadina rhythm like the artificial light, many socio-cultural aspects and so forth. However, several reports of these days indicate human's circadian system is composed of two or more circadian oscillators and SCN is the major circadian oscillator among them like the other mammals. Free-running circadinan period of mankind is about 24 hours rather than about 25 hours, and rest-activity rhythm is polymodal like other species. In addition to that, human may have capcities to change the circadian rhythm as the seasonal changes of daynight schedule. In this article, the author will summarize recent progress of anatomy and physiology of the circadian clock mechanism in humans.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2081-2086
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• 2015

The temperature sensor using ring oscillator is designed by 0.18㎛ CMOS process and the supply voltage is 1.5volts. The temperature sensor is designed by using temperature-independent and temperature-dependent ring oscillators and the output frequency of temperature-independent ring oscillator is constant with temperature and the output frequency of temperature-dependent ring oscillator decreases with increasing temperature. To convert the temperature to a digital value the output signal of temperature-independent ring oscillator is used for the clock signal and the output signal of temperature-dependent ring oscillator is used for the enable signal of counter. From HSPICE simulation results, the temperature error is less than form -0.7℃ to 1.0℃ when the operating temperature is varied from -20℃ to 70℃.