• Journal of the Korean Society of Food Culture
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• v.10 no.3
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• pp.147-154
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• 1995

This study was conducted for the purpose of practice of nutrition education and dietary intake for college students. This survey was carried out through a variety of questionnaires by the subjects which consist of 249 male and 208 female college students in Seoul area. The results obtained were summarized as follows; 1. 75% of the subjects lived in their own houses; the monthly personal expenses were $110{\sim}200$ thousand wons. The appetite of the students who answered was normal in general. The pattern of dietary life shows that they take richer food at dinner than lunch and breakfast. 2. At school, 75% of students ate at the school cafeteria. Among several main dishes, rice was the most favorite food. Most of the subjects ate their lunch between 12 and 1 o'clock, and they spend approximately 11 to 15 minutes. Most of the students did not have lunch on time. The students ate lunch irregularly, because of the class schedule and poor appetite. 3. On weekends and vacations, 56% of the students ate lunch prepared by their mother at home. The two main reasons for skipping lunch during weekends and vacations were late breakfast and poor appetite. The frequency of eating out were $3{\sim}4$ times per week, because of social life and convenience of meal. 4. The majority of college students asked for the improvement of meal quality and the choice of menu in school cafeteria.

• Journal of Korean Society of Transportation
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• v.9 no.1
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• pp.29-46
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• 1991

The purpose of this study is to develop a parking behavior model in prior step for solv-ing parking problems in Pusan C. B. D. The results of this study are as follows; In the C. B. D of Pusan the peak parking time is between 2 and 3 o'clock P. M., and the average parking duration is 237 minutes. It means the use of parking lots is very ineffi-cient. Hence in order to shorten the parking duration, it is very urgent for drivers to chan-ge parking attitude. The walking distance from the parking lots to his destination is below 300∼500m, so the establishment of parking areas and the arrangement of parking lots in C. B. D should be planned on the base of the above walking distance. The model distinguishing between legal and illegal parking behaviors is derived from the binary decision model. The selected model has the correlation rate, η2=0.505 which is relatively high value This result shows that the detetminating judgement on the legal and illegal parking behavior is influenced mutually such factors as driver's occupation parking purpose monthly income distance to his destination averaged parking duration and age.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.155-167
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• 2015

An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a $0.13{\mu}m$ process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.5
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• pp.777-786
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• 2001

In this paper, as one of countermeasure techniques for a frequency selective fading, a digital slope equalizer(DSE) for 64-QAM digital radio relay system is analyzed in terms of principle, channel modeling, and digital implementation. Also computer simulations have been performed for DSE with a complex 13-tap adaptive time domain equalizer chip. It is shown that about 4.5 dB improvement in system signature can be obtained at the channel edge, and a variety of simulated results are reviewed in view of DSE modeling limit, operating frequency, control coefficient, signal constellation, and system signature. Finally, the functions of DSE chip confirmed up to 61 MHz clock operation are illustrated.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.669-679
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• 2013

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1B
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• pp.47-55
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• 2009

In recent network intrusion detection systems, regular expressions are used to represent malicious packets. In order to process incoming packets through high speed networks in real time, we should perform hardware-based pattern matching using the configurable device such as FPGAs. However, operating speed of FPGAs is slower than giga-bit speed network and so, multi-byte processing per clock cycle may be needed. In this paper, we propose a hardware architecture of multi-byte based regular expression pattern matching and implement the pattern matching circuit generator. The throughput improvements in four-byte based pattern matching circuit synthesized in FPGA for several Snort rules are $2.62{\sim}3.4$ times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.892-897
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• 2008

In this paper, a new architecture for digit-parallel/bit-serial GF$(2^m)$ multiplier with low latency is proposed. The proposed multiplier operates in polynomial basis of GF$(2^m)$ and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.3
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• pp.144-148
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• 2001

For the purpose of developing capacitive humidity sensor having interdigit electrodes, interdigit electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thichness. For the development of ASIC, switched capacitor signal conditioning circuits for capacitive humidity sensor were designed and simulated by cadence using 0.25um CMOS process parameters. The signal conditioning circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is 0.4%R.H./$^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of 3%R.H. ${\sim}$ 98%R.H.. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigit electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc..

• Proceedings of the KIEE Conference
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• 1998.07b
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• pp.477-479
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• 1998

This paper presents the results of the field of an improved GPS navigation algorithm. The improved GPS navigation algorithm is a modified Kalman filter which is designed to be ideally suited to car navigation in urban area where lack of GPS visibility is the major problem because of the frequent blockage of the GPS signals by tall buildings and other structures. The method allows the user to estimate its position when the number of visible GPS satellites becomes less than four by using altitude fixing and clock bias estimation techniques. The two estimation techniques are integrated with the Kalman filter in a mutually compensating manner and it is shown that the 3-dimensional position accuracy is well maintained when the number of the visible satellites drops down to two for a reasonable period of time. The post processing results are included to show the improved performance of the modified algorithm over a normal conventional GPS Kalman filter.