• Title/Summary/Keyword: threshold voltage model

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A Study on the Current-Voltage Characteristics of a Short-Channel GaAs MESFET Using a New Linearly Graded Depletion Edge Approximation (선형 공핍층 근사를 사용한 단채널 GaAs MESFET의 전류 전압 특성 연구)

  • 박정욱;김재인;서정하
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.37 no.2
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    • pp.6-11
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    • 2000
  • In this paper, suggesting a new linearly -graded depletion edge approximation, the current-voltage characteristics of an n-type short-channel GaAs MESFET device has been analyzed by solving the two dimensional Poisson's equation in the depletion region. In this model, the expressions for the threshold voltage, the source and the drain ohmic resistance, and the drain current were derived. As a result, typical Early effect of a short channel device was shown and the ohmic voltage drop by source and drain contact resistances could be explained. Furthermore our model could analyze both the short-channel device and the long-channel device in a unified manner.

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A Modeling and Numerical Simulation of Treshold Voltage for Short Channel MOSFET (단 채널 MOSFET의 문턱 전압 모델링과 수치계산)

  • 강정진;이종악
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.15 no.1
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    • pp.9-14
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    • 1990
  • In this paper, I derived a two-dimensional analytical closed-form expression of the threshold voltage for small size MOSFET. The invalid assumptions of constant surface portential or uniform depletion depth were corrected. A comparison between the results of pre-models analyses and the present's proved that this paper's model is quite accurate. Therefore, this model will become a useful design tool for short channel MOSFET.

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A Design of Ion-Implanted GaAs MESFET's Having High Transconductance Characteristics (이온 주입공정에 의한 고 GaAs MESFET의 설계)

  • Lee, Chang Seok;Shim, Gyu-Hwan;Park, Hyung Moo;Park, Sin-Chong
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.6
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    • pp.789-794
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    • 1986
  • The current-voltage characteristics of ion-implanted GaAs MESFET's have been simulated by using the velocity saturation model. Using this model, a MESFET with threshold voltage of -0.5V and transconductance of 460 mS/mm is designed. To implement high transconductance MESFET's, low energy ion-implantation (20 keV) and RTP(Rapid Thermal Process) activation ($575^{\circ}C$, 5sec) processes are required.

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A Light-induced Threshold Voltage Instability Based on a Negative-U Center in a-IGZO TFTs with Different Oxygen Flow Rates

  • Kim, Jin-Seob;Kim, Yu-Mi;Jeong, Kwang-Seok;Yun, Ho-Jin;Yang, Seung-Dong;Kim, Seong-Hyeon;An, Jin-Un;Ko, Young-Uk;Lee, Ga-Won
    • Transactions on Electrical and Electronic Materials
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    • v.15 no.6
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    • pp.315-319
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    • 2014
  • In this paper, we investigate visible light stress instability in radio frequency (RF) sputtered a-IGZO thin film transistors (TFTs). The oxygen flow rate differs during deposition to control the concentration of oxygen vacancies, which is confirmed via RT PL. A negative shift is observed in the threshold voltage ($V_{TH}$) under illumination with/without the gate bias, and the amount of shift in $V_{TH}$ is proportional to the concentration of oxygen vacancies. This can be explained to be consistent with the ionization oxygen vacancy model where the instability in $V_{TH}$ under illumination is caused by the increase in the channel conductivity by electrons that are photo-generated from oxygen vacancies, and it is maintained after the illumination is removed due to the negative-U center properties.

Structure of Low-Power MOS Current-Mode Logic Circuit with Sleep-Transistor (슬립 트랜지스터를 이용한 저 전력 MOS 전류모드 논리회로 구조)

  • Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.15A no.2
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    • pp.69-74
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    • 2008
  • This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

Short Channel Analytical Model for High Electron Mobility Transistor to Obtain Higher Cut-Off Frequency Maintaining the Reliability of the Device

  • Gupta, Ritesh;Aggarwal, Sandeep Kumar;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.2
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    • pp.120-131
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    • 2007
  • A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (T-gate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal work-function and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

Compact Model of a pH Sensor with Depletion-Mode Silicon-Nanowire Field-Effect Transistor

  • Yu, Yun Seop
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.4
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    • pp.451-456
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    • 2014
  • A compact model of a depletion-mode silicon-nanowire (Si-NW) pH sensor is proposed. This drain current model is obtained from the Pao-Sah integral and the continuous charge-based model, which is derived by applying the parabolic potential approximation to the Poisson's equation in the cylindrical coordinate system. The threshold-voltage shift in the drain-current model is obtained by solving the nonlinear Poisson-Boltzmann equation for the electrolyte. The simulation results obtained from the proposed drain-current model for the Si-NW field-effect transistor (SiNWFET) agree well with those of the three-dimensional (3D) device simulation, and those from the Si-NW pH sensor model also agree with the experimental data.

Analysis on I-V of DGMOSFET for Device Parameters (소자파라미터에 대한 DGMOSFET의 전류-전압 분석)

  • Han, Ji-Hyung;Jung, Hak-Kee;Jeong, Dong-Soo;Lee, Jong-In
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.709-712
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    • 2012
  • In this paper, current-voltage have been considered for DGMOSFET, using the analytical model. The Possion equation is used to analytical. Threshold voltage is defined as top gate voltage when drain current is $10^{-7}A$. Investigated current-voltage characteristics of channel length changed length of channel from 20nm to 100nm. Also, The changes of current-voltage have been investigated for various channel thickness and doping concentration using this model, given that these parameters are very important in design of DGMOSFET. The deviation of conduction path and the influence of conduction path on current-voltage have been considered according to the dimensional parameters of DGMOSFET.

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Energy-efficient Custom Topology Generation for Link-failure-aware Network-on-chip in Voltage-frequency Island Regime

  • Li, Chang-Lin;Yoo, Jae-Chern;Han, Tae Hee
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.6
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    • pp.832-841
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    • 2016
  • The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

An Analytical Model for the Derivation of the Ⅰ-Ⅴ Characteristics of a Short Channel InAlAs/InGaAs HEMT by Solving Two-Dimensional Poisson's Equation (2차원 Poisson방정식 풀이에 의한 단 채널 InAlAs/InGaAs HEMT의 전류-전압 특성 도출에 관한 해석적 모델)

  • Oh, Young-Hae;Suh, Chung-Ha
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.5
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    • pp.21-28
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    • 2007
  • In this paper, in order to derive the two-dimensional field effect of n-InAlAs/InGaAs HEMTs, we suggested analytical model by solving the two-dimensional Poisson's equation in both InAlAs and InGaAs regions by taking into account the longitudinal field variation, field-dependent mobility, and the continuity condition of the channel current flowing within the quantum well shaped channel. Derived expressions for long and short channel devices would be applicable to the entire operating regions in a unified manner. Simulation results show that the drain saturation current increases and the threshold voltage decreases as drain voltage increases. Compared with the conventional model, the present model may offer more reasonable explanation for the drain-induced threshold voltage roll-off, the Early effect, and the channel length modulation effect. Furthermore, it is expected that the proposed model would provide more reasonable theoretical basis for analyzing various long and short channel InAlAs/InGaAs HEMT devices.