• 한국초전도ㆍ저온공학회논문지
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• 제11권3호
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• pp.20-25
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• 2009

The quench detection system of the KSTAR (Korea Superconducting Tokamak Advanced Research) primarily uses the resistive voltage measurement due to a quench. This method is to detect the resistive voltage generated by a quench, which is continuously maintained above the preset voltage threshold for a given holding time. As the KSTAR PF (Poloidal Field) coils are operated in the pulse current mode, the large inductive voltages are generated. Therefore the voltage threshold and the quench holding time should be determined by considering both the inductive voltages measured during the operation, and the maximum conductor temperature rise through the quench analysis. In this paper, the compensation methods for minimizing the inductive voltages are presented for the KSTAR PF coils. The quench hot spot analysis of the PF coils was carried out by the analytical and numerical methods for determining the proper values of the quench voltage threshold and the allowable quench protection delay time.

• 대한전자공학회논문지SD
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• 제41권11호
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• pp.1-6
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• 2004

RFIC를 위한 Nanoscale MOSFET에서의 유효 게이트 저항을 직접 추출법으로 추출하여 다양한 게이트 길이에 대해 분석하였다. 추출된 유효 게이트 저항은 비교적 정확하면서 간소화된 모델을 통한 측정결과와 비교하여 10GHz 대역까지 잘 일치함을 확인하였다. 같은 공정기술로 제작된 소자들 중에서 reverse short channel 효과가 생기지 않는 긴 채널 MOSFET 소자의 경우에 일반적인 유효 게이트 저항에서와는 다른 인가전압 및 주파수 종속성을 가짐을 확인하였다. 특히, 문턱전압을 전후하여 주파수에 따라 상이한 결과를 나타내고 있으며, 게이트 인가전압이 문턱전압에 가까울 때 비이상적으로 큰 유효 게이트 저항값을 나타내었다. 이러한 특성은 직접추출법을 사용하는 RF MOSFET 모델링에 있어서 참고해야 할 중요한 특성이 될 것이다.

• 수산해양기술연구
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• 제36권3호
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• pp.186-194
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• 2000

계획어군심지기를 이용하여 자원량을 추정할 경우 해저검출은 매우 중요한 요소이다. 특히 어군이 해저에 가까이 분포하면 할수록, 해저와 어군을 분리하여 책분하는 것은 자원량의 추정정도의 신뢰도를 좌우하게 한다. 본 연구에서는 종래의 해저검출법을 보완하기 위해, 새로운 해저검출법을 개발하여, 그 유효성에 대하여 고찰하였으며, 다음과 같은 결과를 얻었다. 1) 에코레벨의 최대변화점을 이용하여 해저검출을 행한 경우 고정도로, 나아가 레벨 변동과 무관하여 안정한 해저검출법으로서 유효하다. 2) 전압최대변화율법에 의하면, 해저 오프셋는 해저검출위치로부터 0.45m이내에서 설정가능하고, 펄스파형, 해저지형과 음향 빔 등에 의존하여 결정된다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 춘계종합학술대회
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• pp.981-984
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• 2005

본 논문에서는 전하트랩형 SONOS 메모리에서 프로그래밍 동작 후 변화되는 문턱전압을 시뮬레이션에 의하여 구현하고자 한다. SONOS 소자는 질화막내의 트랩 뿐 만아니라, 질화막-블로킹산화막 계면에 존재하는 트랩에 전하를 저장하는 전하트랩형 비휘발성기억소자로서, 기억상태에 따른 문턱전압을 시뮬레이션으로 구현하기위해서는 질화막내의 트랩을 정의할 수 있어야 된다. 그러나 기존의 시뮬레이터에서는 질화막내의 트랩모델이 개발되어 있지 않은 것이 현실이다. 따라서 본 연구에서는 SONOS 구조의 터널링산화막-질화막 계면과 질화막-블로킹산화막 계면에 두개의 전극을 정의하여 프로그램 전압과 시간에 따라서 전극에 유기되는 전하량으로부터 전하트랩형 기억소자의 문턱전압변화를 시뮬레이션 할 수 있는 새로운 방법을 제안한다.

• 전기학회논문지
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• 제60권12호
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• pp.2281-2285
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• 2011

An algorithm for extracting SPICE MOS level 2 model parameters for the high voltage MOSFET DC model is proposed. The optimization method for analyzing the nonlinear data of the current-voltage curve using the Gauss-Newton algorithm is proposed and the pre-process step for calculating the threshold voltage and the mobility is proposed. The drain current obtained from the proposed method shows the maximum relative error of 5.6% compared with the drain current of 2-dimensional device simulation for the high voltage MOSFET.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권9호
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• pp.397-407
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• 2002

A new simulator which predicts the quantum effect in NMOSFET structure is developed. Using the self-consistent method by numerical method, this simulator accurately predicts the carrier distribution due to improved calculation precision of potential in the inversion layer. However, previous simulator uses analytical potential distribution or analytic function based fitting parameter Using the developed simulator, threshold voltage increment and gate capacitance reduction due to the quantum effect are analyzed in NMOS. Especially, as oxide thickness and channel doping dependence of quantum effect is analyzed, and the property analysis for the next generation device is carried out.

• 센서학회지
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• 제28권5호
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• pp.329-333
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• 2019

Solution-processed oxide thin-film transistors (TFTs) have garnered great attention, owing to their many advantages, such as low-cost, large area available for fabrication, mechanical flexibility, and optical transparency. Negative bias stress (NBS)-induced instability of sol-gel IGZO TFTs is one of the biggest concerns arising in practical applications. Thus, understanding the bias stress effect on the electrical properties of sol-gel IGZO TFTs and proposing an effective recovery method for negative bias stressed TFTs is required. In this study, we investigated the variation of transfer characteristics and the corresponding electrical parameters of sol-gel IGZO TFTs caused by NBS and positive bias recovery (PBR). Furthermore, we proposed an effective PBR method for the recovery of negative bias stressed sol-gel IGZO TFTs. The threshold voltage and field-effect mobility were affected by NBS and PBR, while current on/off ratio and sub-threshold swing were not significantly affected. The transfer characteristic of negative bias stressed IGZO TFTs increased in the positive direction after applying PBR with a negative drain voltage, compared to PBR with a positive drain voltage or a drain voltage of 0 V. These results are expected to contribute to the reduction of recovery time of negative bias stressed sol-gel IGZO TFTs.

• 전자공학회논문지B
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• 제32B권10호
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• pp.1280-1285
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• 1995

In this paper the optimized overlap driving scheme for improving the reduction problem of the operating voltage range occured by the overlap driving scheme proposed precedently and increasing the contrast ratio of screen image in the simple matrix LCDs is proposed. The characteristic estimation of the proposed method was performed in a condition that the number of scan electrodes was 120 and the threshold voltage of LC pixel was 2V and the overlap rate of scan signal was varied from 0% to 40% . As a result of estimation compared with the overlap driving scheme proposed precedently, this new method was certified as a method which it could increase the operating voltage range of the LC pixel by 16% in 20% overlap condition and it's operating voltage range was also increased very much with the increase of the overlap rate. Consequently this newly proposed method was certified as a method which it could maintain the improvement effect of the operating characteristics obtained by the overlap driving scheme proposed precedently with the big improvement in the contrast ratio of screen image.

• 전자공학회논문지A
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• 제31A권5호
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• pp.101-105
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• 1994

The EL lamp have been fabricated by screen printing method. the thickness of BaTiO$_3$ dielectric layer and ZnS:Cu phosphor layer was 20 $\mu$m and 40 $\mu$m, respectively. The threshold voltage of green El lamp was 50 $V_{p-p}$ and the maximum brightness was 13.5 $\mu$ W/cm$^2$ at frequency of 700 Hz and the input voltage of 250 $V_{p-p}$. Also when the Rodamin G6 of 0.02 g was doped, the threshold voltage of white EL lamp was 70 $V_{p-p}$ and the maximum brightness was 34 $\mu$W/cm$^2$.

• 대한전자공학회논문지
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• 제26권9호
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• pp.1375-1380
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• 1989

Mobility reduction parameters are extracted using a method based on the exploitatiion of Id-Vg and Gm-Vg characteristics of short channel n-MOSFETs in strong inversion region at room temperature. It is found that the reduction of the maximum field effect mobility, \ulcornerFE,max, with the channel length is due to i) the difference between the threshold voltage and the gate voltage which corresponds to the maximum transconductance, and ii) the channel length dependence of the mobility attenuation coefficient, \ulcorner The low field mobility, \ulcorner, is found to be independent of the channel length down to 0.25 \ulcorner ofeffective channel length. Also, the channel length reduction, -I, the mobility attenuation coefficient, \ulcorner the threshold voltage, Vt, and the source-drain resistance, Rsd, are determined from the Id-Vg and -gm-Vg characteristics n-MOSFETs.