• Journal of the Korean Society of Manufacturing Process Engineers
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• v.19 no.3
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• pp.1-7
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• 2020

Fused filament fabrication (FFF) is a process extruding and stacking materials. PLA materials are one of the most frequently used materials for FFF method of 3D printing. Polylactic acid (PLA)-based materials are among the most widely used materials for FFF-based three-dimensional (3D) printing. PLA is an eco-friendly material made using starch extracted from corn, as opposed to plastic made using conventional petroleum resin; PLA-based materials are used in various fields, such as packaging, aerospace, and medicines. However, it is important to analyze the mechanical properties of theses materials, such as elastic strength, before using them as structural materials. In this study, the reliability of PLA-based materials is assessed through an analysis of the changes in the linear elasticity of these materials under thermal degradation by applying a hyperelastic analytical model.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.1-6
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• 2010

This study presents the preform injection molding and the blow molding of the injection stretch-blow molding process for PET bottles. The numerical analysis of the injection molding and the blow molding of a preform is considered in this paper using CAE with a view to minimize the warpage and the thickness. In order to determine the design parameters and processing conditions in injection/blow molding, it is very important to establish the numerical model with physical phenomenon. In this study, a three dimensional model has been introduced for the purpose and flow simulations of filling, post-filling and cooling process are carried out. The simulations resulted in the warpage in good agreement with the measurements. Also, from the result of numerical analysis, we appropriately predicted the warpage, deformation and thickness distribution along the product walls.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.77-86
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• 2008

The reliability of leaded and lead-free solders of BGA type packages on a printed circuit board was investigated by employing the standard drop test and 4-point bending test. Tested solder joints were examined by optical microscopy to identify associated failure mode. Three-dimensional finite element analysis(FEM) with ANSYS Workbench v.11 was carried out to understand the mechanical behavior of solder joints under the influence of bending or drop impact. The results of numerical analysis are in good agreement with those obtained by experiments. Packages in the center of the PCB experienced higher stress than those in the perimeter of the PCB. The solder joints located in the outermost comer of the package suffered from higher stress than those located in center region. In both drop and bending impact tests, the lead-free solder showed better performances than the leaded solders. The numerical analysis results indicated that stress and strain behavior of solder joint were dependent on various effective parameters.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Journal of the Optical Society of Korea
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• v.10 no.3
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• pp.124-129
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• 2006

We have developed a compact and cost-effective camera module on the basis of wafer-scale-replica processing. A multiple-layered structure of several aspheric lenses in a mobile-phone camera module is first assembled by bonding multiple glass-wafers on which 2-dimensional replica arrays of identical aspheric lenses are UV-embossed, followed by dicing the stacked wafers and packaging them with image sensor chips. This wafer-scale processing leads to at least 95% yield in mass-production, and potentially to a very slim phone with camera-module less than 2 mm in thickness. We have demonstrated a VGA camera module fabricated by the wafer-scale-replica processing with various UV-curable polymers having refractive indices between 1.4 and 1.6, and with three different glass-wafers of which both surfaces are embossed as aspheric lenses having $230{\mu}m$ sag-height and aspheric-coefficients of lens polynomials up to tenth-order. We have found that precise compensation in material shrinkage of the polymer materials is one of the most technical challenges, in orderto achieve a higher resolution in wafer-scaled lenses for mobile-phone camera modules.

• Korean Chemical Engineering Research
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• v.54 no.6
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• pp.723-733
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• 2016

Intensive researches have been focused on the 3-dimensional packaging technology using through silicon via (TSV) to overcome the limitation in Cu interconnection scaling. Void-free filling of TSV by the Cu electrodeposition is required for the fabrication of reliable electronic devices. It is generally known that sufficient inhibition on the top and the sidewall of TSV, accompanying the selective Cu deposition on the bottom, enables the void-free bottom-up filling. Organic additives contained in the electrolyte locally determine the deposition rate of Cu inside the TSV. Investigation on the additive chemistry is essential for understanding the filling mechanisms of TSV based on the effects of additives in the Cu electrodeposition process. In this review, we introduce various filling mechanisms suggested by analyzing the additives effect, research on the three-additive system containing new levelers synthesized to increase efficiency of the filling process, and methods to improve the filling performance by modifying the functional groups of the additives or deposition mode.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.39-45
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• 2012

Three-dimensional integrated circuit(3D IC) technology has become increasingly important due to the demand for high system performance and functionality. In this work, BOE and HF wet etching of Cu line surfaces after CMP were conducted for Cu-Cu pattern direct bonding. Step height of Cu and $SiO_2$ as well as Cu dishing after Cu CMP were analyzed by the 3D-Profiler. Step height increased and Cu dishing decreased with increasing BOE and HF wet etching times. XPS analysis of Cu surface revealed that Cu surface oxide layer was partially removed by BOE and HF wet etching treatment. BOE treatment showed not only the effective $SiO_2$ etching but also reduced dishing and Cu surface oxide rather than HF treatment, which can be used as an meaningful process data for reliable Cu-Cu pattern bonding characteristics.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.7
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• pp.929-933
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• 2010

Four-point bending tests were performed to investigate the interfacial adhesion of Cu-Cu bonding fabricated by thermo-compression process for three dimensional packaging. A pair of Cu-coated Si wafers was bonded under a pressure of 15 kN at $350^{\circ}C$ for 1 h, followed by post annealing at $350^{\circ}C$ for 1 h. The bonded wafers were diced into $30\;mm\;{\times}\;3\;mm$ pieces for the test. Each specimen had a $400-{\mu}m$-deep notch along the center. An optical inspection module was installed in the testing apparatus to observe crack initiation at the notch and crack propagation over the weak interface. The tests were performed under a fixed loading speed, and the corresponding load was measured. The measured interfacial adhesion energy of the Cu-to-Cu bonding was $9.75\;J/m^2$, and the delaminated interfaces were analyzed after the test. The surface analysis shows that the delamination occurred in the interface between $SiO_2$ and Ti.