• Applied Microscopy
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• 제25권2호
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• pp.73-79
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• 1995

The oxidation of silicon wafers is an essential step in the fabrication of semiconductor devices. It is known to induce degradation of electrical properties and lattice strain of Si substrate from thermal oxidation process due to charged interface and thermal expansion mismatch from thermally grown SiO, film. In this study, convergent beam electron diffraction technique is employed to directly measure the lattice strains in Si(100) and $4^{\circ}$ - off Si(100) substrates with thermally grown oxide layer at $1200^{\circ}C$ for three hours. The ratios of {773}-{973}/{773}-{953} Higher Order Laue Zone lines were used at [012] zone axis orientation. Lattice parameters of the Si substrate as a function of distance from the interface were determined from the computer simulation of diffraction patterns. Correction value for the accelerating voltage was 0.2kV for the kinematic simulation of the [012]. HOLZ patterns. The change in the lattice strain profile before and after removal of oxide films revealed the magnitudes of intrinsic strain and thermal strain components. It was shown that $4^{\circ}$ -off Si(100) had much lower intrinsic strain as surface steps provide effective sinks for the free Si atoms produced during thermal oxidation. Thermal strain in the Si substrate was in compression very close to the interface and high concentration of Si interstitials appeared to modify the thermal expansion coefficient of Si.

• Steel and Composite Structures
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• 제17권2호
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• pp.173-184
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• 2014

This study aimed to theoretical calculate the thermal residual stress in continuous SiC fiber reinforced titanium matrix composites. The analytical solution of residual stress field distribution was obtained by using coaxial cylinder model, and the numerical solution was obtained by using finite element model (FEM). Both of the above models were compared and the thermal residual stress was analyzed in the axial, hoop, radial direction. The results indicated that both the two models were feasible to theoretical calculate the thermal residual stress in continuous SiC fiber reinforced titanium matrix composites, because the deviations between the theoretical calculation results and the test results were less than 8%. In the titanium matrix composites, along with the increment of the SiC fiber volume fraction, the longitudinal property was improved, while the equivalent residual stress was not significantly changed, keeping the intensity around 600 MPa. There was a pronounced reduction of the radial residual stress in the titanium matrix composites when there was carbon coating on the surface of the SiC fiber, because carbon coating could effectively reduce the coefficient of thermal expansion mismatch between the fiber and the titanium matrix, meanwhile, the consumption of carbon coating could protect SiC fibers effectively, so as to ensure the high-performance of the composites. The support of design and optimization of composites was provided though theoretical calculation and analysis of residual stress.

• 비파괴검사학회지
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• 제17권2호
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• pp.89-99
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• 1997

단섬유강화금속복합재료는 최근 항공기, 자동차산업에 있어서 관심의 대상이 되고 있는 재료중의 하나이나 재료의 제조 및 성형중에 재료내의 기지재 및 강화재의 열팽창계수의 차이로 인해 재료 내부에 발생되는 열적잔류응력으로 인한 재료 특성의 변화로 실제적인 재료 적용상에 많은 문제점들이 보고되고 있다. 이와 같은 금속복합재료의 잔류응력의 평가에는 몇가지 비파괴적 방법이 적용되고 있으나 그 측정에 많은 어려움이 보고되고 있다. 따라서 금속복합재료의 보다 실제적인 응용을 위하여는 이와 같은 열적잔류응력을 평가하기 위한 이론적모델의 확립이 요구된다. 본 연구에 있어서는 비방향성을 가진 강화재가 2차원 평면 상태로 기지재내에 존재하는 단섬유강화금속복합재료에 있어서 재료에 균일한 온도 변화가 주어질 때 기지재와 강화재의 열팽창계수의 차로 인해 재료 내부에 발생하는 열적잔류응력을 평가, 예측하기 위한 이론적 탄성 모델을 확립하고자 한다. 본 연구에서 해석하고자 하는 이론 모델은 Eshelby의 등가 개재물 방법을 토대로 하고 있으며 과거 제안되고 있는 이론모델을 포함하는 보다 일반성을 가지는 해석 모델로서, 이 해석 모델을 이용하여 열적잔류응력에 미치는 강화재의 체적률, 종횡비, 분포 상태, 분포 cut-off 각도들에 대한 각 인자의 영향을 검토하였다. 그 결과 강화재의 체적률, 종횡비, cut-off 각도들이 강화재의 분포 상태보다도 금속복합재료의 열적잔류응력에 미치는 영향이 현저함을 알 수 있었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

• 한국생산제조학회지
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• 제22권1호
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• pp.168-172
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• 2013

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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• pp.737-739
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• 1998

Gate insulators using various fluoride films were investigated for thin film transistor applications. Conventional oxide containing materials exhibited high interface states, high $D_{it}$ gives an increased threshold voltage and poor stability of TFT. To improve TFT performances, we must reduce interface trap charge density between Si and gate insulator. In this paper, we investigated gate insulators such as such as $CaF_2$, $SrF_2$, $MgF_2$ and $BaF_2$. These materials exhibited an improvement in lattice mismatch, difference in thermal expansion coefficient, and electrical stability MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 0.737%, breakdown electric field higher than 1.7MV/cm and leakage current density of $10^{-6}A/cm^2$. This paper probes a possibility of new gate insulator material for TFT application.

• 마이크로전자및패키징학회지
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• 제6권2호
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• pp.13-21
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• 1999

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances resulting in a high performance and cost-competitive Packaging method. This paper describes the investigation of alternative low cost flip-chip mounting processes using electroless Ni/Au bump and anisotropic conductive adhesives/films as an interconnection material on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed and characterized in mechanical and metallurgical point of view. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with $Ni_3$P precipitation above $300^{\circ}C$ causes an increase of hardness and an increase of the intrinsic stress resulting in a reliability limitation. As an interconnection material, modified ACFs composed of nickel conductive fillers for electrical conductor and non-conductive inorganic fillers for modification of film properties such as coefficient of thermal expansion(CTE) and tensile strength were formulated for improved electrical and mechanical properties of ACF interconnection. The thermal fatigue life of ACA/F flip chip on organic board limited by the thermal expansion mismatch between the chip and the board could be increased by a modified ACA/F. Three ACF materials with different CTE values were prepared and bonded between Si chip and FR-4 board for the thermal strain measurement using moire interferometry. The thermal strain of ACF interconnection layer induced by temperature excursion of $80^{\circ}C$ was decreased with decreasing CTEs of ACF materials.

• Journal of Welding and Joining
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• 제12권4호
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• pp.141-150
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• 1994

The residual stress is inevitably introduced into composites because of the mismatch of the coefficient of thermal expansion, and it is different in each phase. The X-ray technique can detect separately the stress in each phase, so will wield useful information for analyzing the toughening mechanisms of composites. In order to apply the law of mixture to alloy steels with composite microstructures, two phase stainless steel, consisted of ferrite (.alpha.-Fe) and austenite (.gamma.-Fe) structures, was selected. The tensile elastic deformation was loaded, and then the X-ray diffraction technique was used to measure the X-ray elastic constants, the X-ray stress constants and the phase stresses. The law of mixture was investigated and the separation of macrostress and microstress was carried out. The phase stresses (the residual stresses of phase) in each phase, which were measured by X-ray technique, was directly proportional to the applied stress. The macrostress calculated from the phase stresses by using the law of mixture was nearly equal to the applied stress.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 추계학술대회
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• pp.1407-1412
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• 2003

In MEMS devices, packaging induced stress or stress induced structure deformation become increasing concerns since it directly affects the performance of the device. In this paper, deformation behavior of MEMS gyroscope package subjected to temparature change is investigated using high-sensitivity $Moir{\acute{e}}$ interferometry. Using the real-time $Moir{\acute{e}}$ setup, fringe patterns are recorded and analyzed at several temperatures. Temperature dependent analyses of warpages and extensions/contractions of the package are presented. Linear elastic behavior is documented in the temperature region of room temperature to $125^{\circ}C$. Analysis of the package reveals that global bending occurs due to the mismatch of thermal expansion coefficient between the chip, the molding compond and the PCB.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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• pp.122-122
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• 1999

Graphite with its advantages of high thermal conductivity, low thermal expansion coefficient, and low elasticity, has been widely used as a structural material for high temperature. However, graphite can easily react with oxygen at even low temperature as 40$0^{\circ}C$, resulting in CO2 formation. In order to apply the graphite to high temperature structural material, therefore, it is necessary to improve its oxidation resistive property. Silicon Carbide (SiC) is a semiconductor material for high-temperature, radiation-resistant, and high power/high frequency electronic devices due to its excellent properties. Conventional chemical vapor deposited SiC films has also been widely used as a coating materials for structural applications because of its outstanding properties such as high thermal conductivity, high microhardness, good chemical resistant for oxidation. Therefore, SiC with similar thermal expansion coefficient as graphite is recently considered to be a g행 candidate material for protective coating operating at high temperature, corrosive, and high-wear environments. Due to large lattice mismatch (~50%), however, it was very difficult to grow thick SiC layer on graphite surface. In theis study, we have deposited thick SiC thin films on graphite substrates at temperature range of 700-85$0^{\circ}C$ using single molecular precursors by both thermal MOCVD and PEMOCVD methods for oxidation protection wear and tribological coating . Two organosilicon compounds such as diethylmethylsilane (EDMS), (Et)2SiH(CH3), and hexamethyldisilane (HMDS),(CH3)Si-Si(CH3)3, were utilized as single source precursors, and hydrogen and Ar were used as a bubbler and carrier gas. Polycrystalline cubic SiC protective layers in [110] direction were successfully grown on graphite substrates at temperature as low as 80$0^{\circ}C$ from HMDS by PEMOCVD. In the case of thermal MOCVD, on the other hand, only amorphous SiC layers were obtained with either HMDS or DMS at 85$0^{\circ}C$. We compared the difference of crystal quality and physical properties of the PEMOCVD was highly effective process in improving the characteristics of the a SiC protective layers grown by thermal MOCVD and PEMOCVD method and confirmed that PEMOCVD was highly effective process in improving the characteristics of the SiC layer properties compared to those grown by thermal MOCVD. The as-grown samples were characterized in situ with OES and RGA and ex situ with XRD, XPS, and SEM. The mechanical and oxidation-resistant properties have been checked. The optimum SiC film was obtained at 85$0^{\circ}C$ and RF power of 200W. The maximum deposition rate and microhardness are 2$mu extrm{m}$/h and 4,336kg/mm2 Hv, respectively. The hardness was strongly influenced with the stoichiometry of SiC protective layers.