• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1136-1139
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• 2009

Recently, various Ni doping systems and thermal annealing systems have been developed for fabrication of polycrystalline silicon film using SGS (super grain silicon) for medium and largesize AMOLED panels. In this study, we compare the potential of Ni doping systems including ALD (atomic layer deposition), AMD (atmospheric metal deposition), in-line sputter, and crystallization annealing systems including batch type furnace, inline furnace, and RTA (rapid thermal annealing) developed for the SGS method. Additional requirements for those systems to be used for mass production of large AMOLED TVs are suggested based on evaluation results for both poly-Si films and TFT backplanes.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.542-545
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• 1987

THE ELECTRICAL CHARACTERISTICS Of RAPID THERMAL OXIDES AND NITRIDED OXIDES HAVE BEEN INVESTIGATED. R.T.OXIDE FILMS HAVE BEEN PREPARED BY ONLY R.T. OXIDATION OR R.T.OXIDATION AND SUBSEQUENT R.T.ANNEAL. NITRIDED OXIDE FILMS HAVE BEEN PREPARED BY R.T.OXIDATION AND SUBSEQUENT R.T.NITRIDATION.AND CONVENTIONAL OXIDES ALSO HAVE BEEN PREPARED TO COMPARE WITH R.T.P OXIDES. R.T.ANNEALED OXIDES SHOW EXCELLENT BREAKDOWN FIELD. LEAKAGE CURRENT AND TDDB CHARACTERISTICS. ALSO, CAPACITANCE Of R.T NITRIDED OXIDES ARE SUPERIOR BY 10% TO CONVENTIONAL OXIDES, BUT TDDB CHARACTERISTIC ARE POORER THAN OXIDE FILMS.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2003년도 춘계학술대회 발표 논문집
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• pp.18-22
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• 2003

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by grinding, lapping and polishing. The surfaces of sapphire wafers were mechanically affected by residual stress and surface default. This mechanical stress and strain can be cured by thermal anneal ing process. The sapphire crystalline wafers were annealed at $1100~1400^{\circ}C$ and then characterized by double crystal X-ray diffraction. The sample showed good quality of crystalline wafer surface wi th full width at hal f maximum of 16 arcsec for the 4-hour heat-treatment at $1300^{\circ}C$.

• 전자공학회논문지A
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• 제30A권1호
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• pp.31-43
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• 1993

Thermal behavior and $O_{2}$ plasma effects on residue and penetrated impurities formed by reactive ion etching (RIE) in CHF$_{3}$/C$_{2}$F$_{6}$ have been investigated using X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS) techniques. Decomposition of polymer residue film begins between 200-300.deg. C, and above 400.deg. C carbon compound as graphite mainly forms by in-situ resistive heating. It reveals that thermal decomposition of residue can be completed by rapid thermal anneal above 800.deg. C under nitrogen atmosphere and out-diffusion of penetrated impurities is observed. The residue layer has been removed with $O_{2}$ plasma exposure of etched silicon and its chemical bonding states have been changed into F-O, C-O etc.. And $O_{2}$ plasma exposure results in the decrease of penetrated impurities.

• 대한전기학회논문지
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• 제45권2호
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• pp.242-248
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• 1996

The properties of TiN/TiSi$_{2}$ bilayer formed by a rapid thermal annealing is investigated when thin SiO$_{2}$ film exists at the Ti-Si interface. The competitive reaction for the TiN/TiSi_2 bilayer occurs above 600 .deg. C. The thickness of the TiSi$_{2}$ layer decreases with increasing SiO$_{2}$ film thickness and also decreases with increasing anneal temperture When the competitive reaction for the TiN/TiSi$_{2}$ bilayer is occured by rapid thermal annealing, the composition of TiN layer represents TiN$_{x}$O$_{y}$ due to the SiO$_{2}$ layer at the Ti-Si interface but the structures of the TiN and TiSi$_{2}$ layers were not changed.d.d.

• 한국전기전자재료학회논문지
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• 제31권4호
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• pp.198-202
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• 2018

In this work, we have investigated the effect of a 30-min thermal anneal at $550^{\circ}C$ on the electrical characteristics of neutron-irradiated 4H-SiC MOSFETs. Thermal annealing can recover the on/off characteristics of neutron-irradiated 4H-SiC MOSFETs. After thermal annealing, the interface-trap density decreased and the effective mobility increased in terms of the on-characteristics. This finding could be due to the improvement of the interfacial state from thermal annealing and the reduction in Coulomb scattering due to the reduction in interface traps. Additionally, in terms of the off-characteristics, the thermal annealing resulted in the recovery of the breakdown voltage and leakage current. After the thermal annealing, the number of positive trapped charges at the MOSFET interface was decreased.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 D
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• pp.1830-1832
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• 1999

고에너지 이온주입(1)에 기인한 격자 손상 발생 및 열처리에 따라 이들의 회복이 어느정도 가능한지에 대하여 측정 및 분석방법을 통하여 조사하였다. 그리고 본 실험에서는 이온주입시 형성되는 빈자리 결함(Vacancy defect)과 격자간 결함(interstitial defect)의 재결할(recombination)을 이용 점결합(point defect)를 감소 시킬 수 있는 effective RTA조건을 설정하여 well 특성을 개선하고자 하였다. 8inch p-type Si(100)기판에 pad oxide 100A을 형성한 후 NMOS 형성하기 위해 vtn${\sim}$p-well과 PMOS 형성을 위해 vtp$\sim$n-well을 이온주입 하였다. Mev damage anneal은 RTA(2)(Rapid Thermal Anneal)로 $1000\sim1150C$ 온도에서 $15\sim60$초간 spilt 하여 실험후 suprem-4 simulation data를 이용하여 실제 SIMS측정 분석결과를 비교하였으며 이온주입에 의해 발생된 격자손상이 열처리후 damage 정도를 알아보기 위해 T.W(Therma-Wave)을 이용하였으며 열처리후 면저항값은 4-point probe를 사용하였다. 이온주입후 열처리 전,후에 따른 불순물 분포를 SIMS(Secondary ion Mass Spectrometry)를 이용하여 살펴보았다. SIMS 결과로는 열처리 온도 및 시간의 증가에 따라서 dopant확산 및 활성화는 큰차이는 보이지 않고 오히려 감소하는 경향을 볼 수 있으며 또한 접합깊이와 농도가 약간 낮아지는 것을 볼 수 있었다. 결점(defect)을 감소시키기 위해서 diffusivity가 빠른 임계온도영역($1150^{\circ}C$-60sec)에서 RTA를 실시하여 dopant확산을 억제하고 점결점(point defect)의 재결합(recombination)을 이용하여 전위 (dislocation)밀도를 감소시켜 이온주입 Damage 및 면저항을 감소 시켰다. 이와 같은 특성을 process simulation(3)(silvaco)을 통하여 비교검토 하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 D
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• pp.1352-1354
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• 1998

$LiNbO_3$ transistor showed relatively stable characteristic, low interface trap density, and large remanent polarization. This paper reports ferroelectric $LiNbO_3$ thin films grown directly on p-type Si(100) substrates by 13.56 MHz rf magnetron sputtering system for FRAM applications. To take advantage of low temperature requirement for growing films, we deposited $LiNbO_3$ films lower than $300 ^{\circ}C$. RTA(Rapid Thermal Anneal) treatment was performed for as-deposited films in an oxygen atmosphere at $600^{\circ}C$ for 60 sec. We learned from X-ray diffraction that the RTA annealed films were changed from amorphous to poly-crystalline $LiNbO_3$ which exhibited (012), (015), and (022) orientations. The I-V characteristics of $LiNbO_3$ films before and after anneal treatment showed that RTA improved the leakage current of films. The leakage current density of films decreased from $10^{-5}$ to $10^{-7} A/cm^2$ at room temperature measurement. Breakdown electric field of the films exhibited higher than 500 kV/cm. The C-V curves showed the clockwise hysteresis represents ferroelectric switching characteristics. From C-V curves, we calculated dielectric constant of thin film $LiNbO_3$ as 27.5 which is close to that of bulk value.

• 센서학회지
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• 제26권6호
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• pp.438-444
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• 2017

In this paper, we focus on optimization of the in-situ phosphorous (P) doping of low-pressure chemical vapor deposited (LPCVD) poly Si resistors for obtaining near-zero temperature coefficient of resistance (TCR) at temperature range from 25 to $600^{\circ}C$. The deposited poly Si films were annealed by rapid thermal anneal (RTA) process at the temperature range from 900 to $1000^{\circ}C$ for 90s in nitrogen ambient to relieve intrinsic stress and decrease the TCR in the poly Si layer and get the Ohmic contact. After the RTA process, a roughness of the thin film was slightly changed but the grain size and crystallinity of the thin film with the increase in anneal temperature. The film annealed at $1,000^{\circ}C$ showed the behavior of Schottky contact and had dislocations in the films. Ohmic contact and TCR of $334.4{\pm}8.2$ (ppm/K) within 4 inch wafer were obtained in the measuring temperature range of 25 to $600^{\circ}C$ for the optimized 200 nm thick-poly Si film with width/length of $20{\mu}m/1,800{\mu}m$. This shows the potential of in-situ P doped LPCVD poly Si as a resistor for pressure sensor in harsh environment applications.

• 한국전기전자재료학회논문지
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• 제17권12호
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• pp.1283-1288
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• 2004

Metal-ferroelectric-insulator-semiconductor(WFIS) capacitors using rapid thermal annealed LiNbO$_3$/AlN/Si(100) structure were fabricated and demonstrated nonvolatile memory operations. The capacitors on highly doped Si wafer showed hysteresis behavior like a butterfly shape due to the ferroelectric nature of the LiNbO$_3$ films. The typical dielectric constant value of LiNbO$_3$ film in the MFIS device was about 27, The gate leakage current density of the MFIS capacitor was 10$^{-9}$ A/cm$^2$ order at the electric field of 500 kV/cm. The typical measured remnant polarization(2P$_{r}$) and coercive filed(Ec) values were about 1.2 $\mu$C/cm$^2$ and 120 kV/cm, respectively The ferroelectric capacitors showed no polarization degradation up to 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulses of 1 MHz. The switching charges degraded only by 10 % of their initial values after 4 days at room temperature.e.