• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.673-675
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• 2011

본 논문은 GHz 대역 소자 응용을 위한 프로그램 가능 보상 회로를 제안한다. 이러한 회로는 5.2GHz대에서 동작하는 고주파 회로의 칩 제작과정에서 예기치 않게 발생한 미세한 PVT (공정, 전압, 온도) 변동을 검출하여 미세 변동된 회로 성능 변수들을 자동으로 보상한다. 자동으로 보상 가능한 고주파 회로 성능 변수들은 중요한 요소인 입력 임피던스, 전압이득과 잡음지수를 포함한다. 이러한 회로는 미세 변동을 자동으로 보상할 수 있도록 고주파 신호를 직류 신호로 변환하는 DFT (Design-for-Testability) 회로를 포함한다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 추계학술대회
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• pp.718-721
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• 2010

본 논문은 고주파 시스템-온-칩 응용을 위한 자동 보상 시스템을 제안한다. 이러한 시스템은 고주파 회로 칩 제작과정에서 예기치 않게 발생한 미세한 PVT(공정, 전압, 온도) 변동으로 인한 회로 성능 변수들의 미세변동을 검출하여 이를 자동으로 보상한다. 자동으로 보상 가능한 고주파 회로 성능 변수들은 중요한 요소인 입력 임피던스, 전압이득 및 잡음지수를 포함한다. 이러한 시스템은 미세 변동을 자동으로 보상할 수 있도록 고주파 신호를 직류 신호로 변환하는 DFT(Design-for-Testability) 회로를 포함한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.329-332
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• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• 마이크로전자및패키징학회지
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• 제5권2호
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• pp.21-26
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• 1998

대용량, 고속데이터 처리가 요구되는 System 개발은 이들의 복잡하고 고기능의 회 로 구현이 가능하냐에 달려 있고 또한 이들고기능 요구를 가장 잘 만족할수 있는 패키지는 MCM 이라 할 수있다. 시스템의 고속화, 소형화는 회로의 복잡성을 요구하는 있는 이를 패 키지로 구현하는 MCM은 시험성 확보에 심각한 문제점으로 나타나고 있다. 본 논문에서는 고밀도 구조의 MCM 기판에 대한 Interconnetion Line 시험검증을 위한 Flying Prober의 적 용 및 모듈 패키징 공정에 대한 조립성 검증을 위한 BST에 대해 설명한다. 연구에 사용된 MCM 모듈은 MCM-D 공정으로 제작되었으며 31um 신호선폭, 50um Via Hole Dia. 5신호 선층 5절연층 및 455 Net의 기판으로절연층은 Dow chemical의 BCB-4024/4026을 적용하였 다. 조립은 3 ASIC, 24소자 실장 및 2000 Wire Bonding으로 이루어지며 패키지는 방열특성 을 고려한 BGA(491 I /O,50mil pitch)를 개발하여 사용하였다. MCM 기판의미세패턴으로 구성된 Interconnection Line에 대해 Fine Ptich Probing이 가능한 Flying Prober를 사용하 여 평가하였으며 BST를 이용하여 실장소자의 KGD평가 및 능동, 수동소자가 실장된 MCM Package의 조립시험성을 확보할수 있었다.

• 한국전자통신학회논문지
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• 제3권4호
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• pp.228-232
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• 2008

For the past several years, many countries have passed or have recommended legislation making it illegal to use in-hand mobile phones while driving and several manufacturers have released car kit solutions enabling hands-free operation of the mobile phone. But an automobile environment can pose extremely harsh physical conditions impacting audio quality, safety, and reliability. This article introduced a Car Kits that provided a total entertainment and telematics solution, which support all current features within the constraints of low power consumption, form factor, price, ease-of-use, manufacture ability, testability and high total quality.

• 전기학회논문지
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• 제58권1호
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1963-1964
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• 2008

Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. We propose a new technique to re-design about clock operation. This technique propose about low power operation of scan clock and saved time of test operation.

• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.7-13
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• 1997

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns sifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can e applied by scan shifting and then pulsing a system clock like the full scan but with much les scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.

• 대한전자공학회논문지
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• 제24권3호
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• pp.517-526
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• 1987

This paper proposes a new testable design for Zipper CMOS circuits. This design provides an additional feedback loop (called self oscillation loop) whichin the circuit, for testability. The circuit is tested only by observing the oscillation on the loop. The design can be applied to the multistage as well as the single stage, and can detect multiple faults which are undetectable by the conventional testing method. The application and evaluation of test patterns become easy and fault-free responses are not necessary. If the conventional testing method is applied to the sequential Zipper CMOS circuit with the LSSD design technique, it has the serious defect that the initial value may change due to intermediate test patterns and much time taken to apply the necessary test patterns. By using the proposed design, however, the sequential Zipper CMOS circuit with the LSSD design technique can be easily tested without such a defect. Also, the validity of the design is verified by performing the circuit level simulation.

• 대한전자공학회논문지
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• 제24권3호
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• pp.527-534
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• 1987

This paper proposes a new syndrome-testable design method for large MOSPLA's. In the conventional syndrome test method, the testing array circuit for testability is added but it has the defect that the circuit gives effect on the normal operation of the basic PLA circuit. Therefore, by adding the shift registers to the product lines of the basic MOSPLA's this defect is eliminated and the number of test patterns is decreased. In order to reduce the number of fault free syndromes to be predetermined, also, one output line, which is connected to all product lines is added. Therefore the number of output lines be observed is decreased. And the analytical method to compute fault free syndromes is presented. By unsing this method, the time and the effort to compute the syndromes are decreased.