• Journal of Korea Multimedia Society
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• v.10 no.10
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• pp.1260-1270
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• 2007

Testing and diagnosis of analog circuits(or mixed-signal circuits) continue to be a hard task for test engineers and efficient test methodologies to solve these problems are needed. This paper proposes a novel analog circuits test technique using time slot specification (TSS) based built-in current sensors (BICS). A technique for location of a fault site and separation of fault type based on TSS is also presented. The proposed built-in current sensors and TSS technique has high testability, fault coverage and a capability to diagnose catastrophic faults and parametric faults in analog circuits. In order to reduce time complexity of test point insertion procedure, external output and power nodes are used for test points and the current sensors are implemented in the automatic test equipment(ATE). The digital output of BICS can be easily combined with built-in digital test modules for analog IC test.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2731-2740
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• 2012

ASIC(application specific integrated circuit) process is a set of various technologies for fabricating a chip. Generally there have been many researches for RTL design, synthesis, floor plan & routing, low power scheme, clock tree synthesis, and testability which are widely researched in recent. In this paper we propose a new methodology of power strap routing in basis of design experience and experiment. First the power strap for vertical VDD and VSS and horizontal VDD and VSS is routed, and then after the problems which are generated in this process are analyzed, we propose a new process for resolving them. For this, the strap guide is inserted to protect the unnecessary strap routing and dumped for next steps. Next the unnecessary power straps which are generated the first inserting process are removed, and the pre-routing is performed for the macro cells. Finally the resultant power straps are routed using the dumped routing guide. Through the proposed process we identified the efficient and stable route of the power straps.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.4
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• pp.28-39
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• 2007

This paper presents a programmable RF DFT (Radio Frequency Design-for-Testability) circuit for low noise amplifiers. We have developed a new on-chip RF DFT circuit that measures RF parameters of low noise amplifier (LNA) using only DC measurements [1, 2]. This circuit is extremely useful for today's RFIC devices in a complete RF transceiver environment. The DFT circuit contains test amplifier with programmable capacitor banks and RF peak detectors. The test circuit utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the mathematical equations. Our on-chip DFT circuit can be self programmed for 1.8GHz, 2.4GHz and 5.25GHz low noise amplifiers for GSM, Bluetooth and IEEE802.11g standards. The circuit is simple and inexpensive.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.15-24
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• 2009

This paper proposes an effective low power BIST architecture using the pattern mapping method for 100% fault coverage and the transition freezing method for making high correlative low power patterns. When frozen patterns are applied to a circuit, it begins to find a great number of faults at first. However, patterns have limitations of achieving 100% fault coverage due to random pattern resistant faults. In this paper, those faults are covered by the pattern mapping method using the patterns generated by an ATPG and the useless patterns among frozen patterns. Throughout the scheme, we have reduced an amount of applied patterns and test time compared with the transition freezing method, which leads to low power dissipation.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.640-654
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• 1996

This paper presents a synthesis method for multi-level Reed-Muller circuits using BDDs(Binary Decision Diagrams). The existing synthesis tool for Reed circuits, FACTOR, is not appropriate to the synthesis of large circuits because it uses matrix (map-type) to represent given logic functions, resulting in the exponential time and space in number of imput to the circuits. For solving this problems, a syntheisis method based on BDD is presented. Using BDDs, logic functions are represented compactly. Therefor storage spaces and computing time for synthesizing logic functions were greatly decreased, and this technique can be easily applied to large circuits. Using BDD representations, the proposed method extract best patterns to minimize multi-level Reed Muller circuits with good performance in area optimization and testability. Experimental results using the proposed method show better performance than those using previous methods〔2〕. For large circuits of considering the best input partition, synthesis results have been improved.

• Women's Health Nursing
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• v.26 no.2
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• pp.120-130
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• 2020

This study aimed to evaluate Cox's interaction model of client health behavior (IMCHB) as used in studies on women's health. Using keyword combinations of "women" and "IMCHB" or "interaction model of client health behavior," we searched the PubMed, MEDLINE, Embase, and RISS databases for studies on the promotion of women's health published from January 2009 to April 2019. Finally, 11 studies were selected and evaluated according to seven criteria for theory evaluation, which combined Fawcett's theory evaluation criteria and Chinn and Kramer's criteria. We found that the IMCHB corresponds to a verifiable practical level of a middle-range theory, although it may be partially abstract. It contains all four concepts of the metaparadigm of nursing, in terms of a holistic philosophical approach. A theoretical evaluation demonstrated that the IMCHB has significance, generality, testability, empirical adequacy, and pragmatic adequacy for nursing practice and research. However, the lack of clear conceptual definitions and the presence of complex relationships among concepts resulted in a lack of internal consistency and parsimony. According to an in-depth verification through a review of the literature, the IMCHB has been used as a health promotion intervention strategy for various populations of women and has led to useful results in nursing practice. The IMCHB was confirmed to be a suitable theory for experimental and clinical research. Future research can build on this middle-range theory for women's health research and practice.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.6
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• pp.473-480
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• 2021

In this paper, We analyze and present improvements to problems in software quality through Static Analysis for Open Source, which is widely used as the Flight Controller software for small unmanned aerial vehicle drones. MISRA coding rules, which are widely applied based on software quality, have been selected. Static analysis tools were used by LDRA tools certified international tools used in all industries, including automobiles, railways, nuclear power and healthcare, as well as aviation. We have identified some safety-threatening problems across the quality of the software, such as structure of open source modules, analysis of usage data, compliance with coding rules, and quality indicators (complexity and testability), and have presented improvements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.53-60
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• 2004

This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.4 no.1
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• pp.29-65
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• 2009

This study is The Effect of the on the purchase behavior of the Software Quality. To have purchased the software in a Consumer surveys were conducted. The following is a summary of results of this research. First, the software quality and significant consumer purchasing behavior (+) of influence. Functionality, usability, portability of software quality attributes the impulse buying and buy more of both the (+) showed the influence. Second, software quality is urge consumers to purchase significant (+) of influence. Functionality, reliability, usability, portability of software quality (+) showed the influence. Third, the software quality In the consumer buy more significant Chung (+) showed the influence. Software quality, functionality, usability, portability name (+) influence. In conclusion, the quality of the software in consumer purchasing behavior (+) were of significant influence. In particular, factors that functionality, usability factors, portability factor in the relatively large influence on the purchasing behavior. Software technology development, planning, development, testing, and in each step must keep in mind the following. First, the software, when used in certain conditions, Inherent ability to meet the needs and requirements set forth to provide the appropriate functionality and accuracy as the ability of software products each other with the capabilities to the effective and thorough security features should be required. Second, software, a user-specified criteria to use in understanding and learning, and must, and the ability to prefer. Software for users to understand and easy to use, whether the check. In particular, understanding the interface, Help understanding, understand the input and output data, and interface consistency, the user information, the message must be equipped and easy to understand. In addition, ease of learning to be self-learning, and help ease of access shall be required. Third, in certain circumstances, a different environment to transfer be equipped with the functionality of the software. Applying data structures and application environment, helping transplant convenience must keep in mind sex.