• Journal of the Korean Society for Aviation and Aeronautics
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• v.19 no.4
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• pp.18-23
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• 2011

Generally, the digital circuit card can be tested by automatic test equipment using LASAR(Logic Automated Stimulus and Response). This paper proposes the ROM data extracting algorithm which can test the digital circuit card that consists usually ROMs. We are implemented of the proposed fault detecting program by LabWindow/CVI 8.5 and the digital automatic test instrument with NI-VXI(National Instrument - Versa Bus Modular Europe eXtentions for Instrumentation) card. We also make an interface circuit board connecting the digital test instrument and the digital circuit card. It shows the good performance of getting the data from ROMs.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.10-21
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• 1998

In this paper, we analyze the problems of conventional and previous mehtod on delay test method in IEEE 1149.1. To solve them, we propose two kinds of delay test architectures. One is called ARCH-C, is for combinatonal circuit, and the other is ARCH-S, for clocked sequential circuit. ARCH-C is able to detect delay defect of 0.5 $T_{tck}$ or 1 $T_{tck}$ size. And ARCH-C have a fixed and small amount of hardware overhead, on the contrary preious method has a hardware overhead on the dependent of CUT. This paper discusses weveral problems of Delay test on IEEE 1149.1 for clocked sequential circuit. We suggest the method called ARCH-S, is based on a clock counting technique to generate continuous clocked input of CUT. the simulation results ascertain the accurate operation and effectiveness of the proposed architectures.res.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1783-1785
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• 2001

With the 4-MJ synthetic testing facilities completed, KERI can perform the circuit breaker testing up to 420 kV, 50 kA ratings. The short-line fault test is one of the necessary test items which are required for the circuit breaker, and in order to perform the short-line fault test KERI(Korea Electrotechnology Institute) has used the "new artificial line" which has small dimension and is easy to generate the saw-tooth wave. This paper describes the following items of the new artificial line. -Description of 4-kinds of artificial lines and determination of the circuit parameter of artificial line. -TRV characteristics of saw-tooth waves for each circuit. -KERI's artificial line.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.10-13
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• 2003

6.6㎸rms/200Arms DC reactor type superconducting fault current limiter (SFCL) has been developed. This paper deals with the manufacture and short-circuit test of the SFCL. DC reactor was the HTS solenoid coil whose inductance was 84mH. AC/DC power converter was performed as the dual-mode operation. The short-term run(1 sec) and short-circuit test of this SFCL was performed successfully. The experimental results have a similar tendency to the simulation results. In short-circuit test, at 2 cycles after the fault, fault current limitation rate was about 30％.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1186-1188
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• 1999

When we perform the test related to the power distribution system such as artificial fault test, protective coordination test, distribution automation test in short length test line, Lumped Constant Circuit, a kind of variable impedance, should be attached to the test line in order to make it equivalent to a real line in length electrically. In this paper we designed the positive sequence and zero sequence Lumped Constant Circuit with optimized inductor and resister for the modification of long, 16km, distribution line, when they are attached to the short, 4km, distribution test line.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.140-148
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• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.328-332
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• 2010

The SLF(Short Line Fault) breaking capability test for high voltage class $SF_6$ GCB(Gas Circuit Breaker) was conducted. Simplified LC resonant circuit test facility was used for SLF breaking test. During test, Test current was measured by Rogwski coil and arc voltage was measured by voltage divider. Arc conductance was calculated by using these test results before 200ns at current zero. Critical arc conductance value at rated voltage 145kV class is about 2.3mS regardless of breaking current magnitude and arc conductance value at rated voltage 170kV class is about 2.6mS.

• ETRI Journal
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• v.31 no.2
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• pp.209-214
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• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• Progress in Superconductivity and Cryogenics
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• v.3 no.2
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• pp.32-38
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• 2001

A 30[kVA] superconducting generator (SCG) is built and tested at Korea Electrotechnology Research Institute (KERI) in Korea. This superconducting generator has an air-gap winding instead of the typical steel teeth structure. The rotor has 4 field coils of race-track type with NbTi superconducting wired. The rotor is composed of two dampers and a liquid helium composed of two dampers and a liquid helium container in which the field poles reside. The space between the outermost damper and the container is vacuum insulated. A ferrofluid seal is used between the stationary part connected to the couping and the rotor. A helium transfer coupling(HTC) has 3 passages of the recovered heilum gas and a gas flow control system. The open circuit test and sustained short circuit test are preformed to obtain the open circuit characteristics (OCC) and short circuit characteristics (SCC) Also. the test results usder the light load (up to 3.6[kW]) are given. The structure, manufacturing and basis test of the 30[kVA]SCG are discussed.