• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.1
• /
• pp.15-22
• /
• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.29 no.8
• /
• pp.23-31
• /
• 2015

This paper proposes an advanced distance relaying based on the DC offset removal filter to minimize the effects of DC offset on a double circuit transmission line. The proposed DC offset removal filter uses only one cycle of data for phasor extraction computation, which does not need to preset the time constant of the DC offset component. This proposed distance relaying uses not only the residual current of the faulted circuit but also mutual current of the healthy adjacent circuit. A series of off-line test results using ATP simulation data show the effectiveness of the an advanced distance relaying.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.154-157
• /
• 2004

With the need of high-speed and mass data transmission, optical communication system requires the growth of optical components. Waveguide photodiodes(WGPDs) are introduced and circuit models of WGPD and submodule are required for the optical receiver application. In this paper, the circuit models of WGPD and submodule are investigated and modeling results are derived by PEEC methodology. The s-parameters are measured for the test structures of WGPD and submodule and the equivalent circuit models are examined. The modeling results agreed well with the measured data and can present a reasonable physical representation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.16 no.1
• /
• pp.67-75
• /
• 2002

This paper presents a PLD design of Gray Mode Graphic STN LCD drive circuit using PC interface. The proposed LCD drive circuit doesn\`t use microprocessor for the convenience of users. Thus, the LCD drive circuit can transfer efficiently image data created under PC to LCD. The LCD drive circuit which is modelled in schematic capture, AHDL and VHDL is simulated in functionally through the use of ALTERA MAX+PLUS II. Also, timing simulation is performed by ALTERA EPM7192SQC160-15 PLD implementation. The PC interface part have been programmed in MS-Visual C++ 6.0. The validity and efficiency of the proposed LCD drive circuit have been verified by test board. After comparing this LCD drive circuit to specify it was verified that the developed LCD drive circuit showed good performances, such as convenience of users, low cost.

• The KIPS Transactions:PartA
• /
• v.9A no.1
• /
• pp.53-60
• /
• 2002

This paper describes a Gray Mode Graphic STN LCD drive circuit using USB interface. The drive circuit using USB interface can highly transfer image data created under PC t LCD. Hence, the LCD drive circuit doesn't use microprocessor for the convenience of users. The proposed LCD drive circuit part have been verified by simulation and by ALTERA EPF10K10TC144-3 FPGA implementation in VHDL. The USB interface part have been programmed in MS-Visual C++ 6.0. The validity and efficiency of the proposed LCD drive circuit have been verified by test board. After comparing this LCD drive circuit to specify it was verified that the developed LCD drive circuit showed good performances, such as convenience of users, low cost.

• Smart Media Journal
• /
• v.12 no.1
• /
• pp.17-23
• /
• 2023

Design-For-Security (DFS) methodology is to protect integrated circuits from physical attacks, and that can be implemented by adding a security circuit to detect abnormal external access. Among the abnormal accesses called invasive attack, microprobing and FIB circuit editing are classified as the most powerful methods because they have direct access. Microprobing deliberately inject defects into the wire of circuit through probes, or reads and changes data. FIB circuit editing is methods of reconnecting or destroying circuits to neutralize security circuits or to access data. Previous DFS methodology have responded to the attacks by detecting arrival time asymmetry between the two signals or by comparing input/output data based on encrypted communication. This study conducted to reduce hardware overhead, and the proposed circuit detects the reflected signal asymmetry generated through probe or FIB circuit editing and detects the attacks through comparison. Since the proposed security circuit reduces the size and test cycle of the circuit compared to previous studies, the cost used for security can be reduced.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.7
• /
• pp.4849-4854
• /
• 2015

It has been often occurred for the outside components(BU, SVaC, DB) of UM71c AF track circuits to be broken down caused by some pieces of falling ice in the winter time or by infrastructure repairing equipments while facility maintenance works since 2004, opening of Kyeongbu High Speed Rail Express. In this paper, we proposed that we could move the outside components of UM71c track circuit out of wayside from present place. Then we can assure that the life time of those components would be extended. So we simulated the electrical characteristics by changing cable length using MATLAB Simulinks and we designed the compensation capacitor. Also, we obtained the same results as those of simulation by field demonstration test on site. The design specifications obtained from this field verification test could be applied in the absent section of track circuit, if only have a little more intensified research to compensate changed electrical characteristics and to redesign inner impedance of the track circuit.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.11
• /
• pp.124-129
• /
• 2013

This paper proposes a high-performance vector inner product calculation circuit for real-time object recognition based on SVM algorithm. SVM algorithm shows a higher detection rate than other object recognition algorithms. However, it requires a huge amount of computational efforts. Since vector inner product calculation is one of the major operations of SVM algorithm, it is important to implement a high-performance vector inner product calculation circuit for real-time object recognition capability. The proposed circuit adopts the pipeline architecture with six stages to increase the operating speed and makes it possible to recognize objects in real time based on SVM. The proposed circuit was described in Verilog HDL at RTL. For silicon verification, an MPW chip was fabricated using TSMC 180nm standard cell library. The operation of the implemented MPW chip was verified on the test board with test application software developed for the chip verification.

• Journal of the Korean Data and Information Science Society
• /
• v.15 no.4
• /
• pp.935-943
• /
• 2004

Most of the accelerated life tests deal with tests that use only one accelerating variable and no other explanatory variables. Frequently, however, there is a test to use more than one accelerating or other experimental variables, such as, for examples, a test of capacitors at higher than usual conditions of temperature and voltage, a test of circuit boards at higher than usual conditions of temperature, humidity and voltage. A accelerated life test is extended to M-level stress accelerated life test with k-stress variables. The optimal design for Weibull distribution is studied with k-stress variables.

• Proceedings of the KIEE Conference
• /
• 1983.07a
• /
• pp.98-100
• /
• 1983