• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1968-1971
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• 2002

In this paper, we have presented a test- ing method for a kind of asynchronous circuits. Tar- get circuit model is the 3D machine that is one of the most successful implementation of extended burst-mode (XBM) machines. We present a high-level test generation method for the 3D machine using the specification of the circuit. We also present a gate-level test pattern generation method using a synchronous test pattern generator. Experimental results show that the combination of the above two methods achieves high fault coverage over 3D machines and saves test generation time.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.1111-1113
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• 2000

This paper presents the calculation method for the equivalent-circuit parameters and torque characteristics of squirrel-cage induction motors. The measurement of motor parameters were calculated by the stator resistance test, the blocked rotor test and no load test to T type equivalent-circuit. Especially, this paper describes the test results obtained by using hall sensor and strain gauge for the current and torque characteristics of induction motors. Three-phase squirrel-cage induction motor which has 1[hp] was used to the test and the parameters obtained by the test were compared with the maker parameters.

• Journal of Power Electronics
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• 제6권1호
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• pp.1-7
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• 2006

This paper is a record of the study on a high efficiency and high power chopper based on the new soft switching method QRAS (Quasi~resonant Regenerating Active Snubber) designed for a Fuel Cell Electric Vehicle (FCEV). This power chopper is basically proposed for 25kHz soft switching. To confirm the practicality and effectiveness of the converter, the fabrication of a prototype-model using IGBTs was completed. Additionally, a 8kW rating test, a light load test, a current discontinuous mode test and a stable operation resonance test was completed. The circuit geometry, the basic operation, and the 8kW one-tenth-prototype test results are reported with a $97.5\%$ efficiency measurement.

• 한국전자파학회논문지
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• 제24권4호
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• pp.436-447
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• 2013

본 논문에서는 IC(Integrated Circuit) 전자파 전도내성 시험 방법인 BCI(Bulk Current Injection)와 DPI(Direct Power Injection)를 이용하여 1.8 V I/O 버퍼에 대한 IC 전자파 전도내성을 시험하였다. IC 전자파 전도내성 시험을 회로 해석기를 사용하여 시뮬레이션 할 수 있는 등가회로 모델(model)을 개발하고 검증하였다. BCI와 DPI의 주파수에 따른 forward 전력을 비교한 결과는 주파수 성분에 따라 실제 IC에 도달하는 전자파(electromagnetic, EM) 노이즈의 양이 제한됨을 보여준다. 시뮬레이션을 통해, 가해지는 RF(Radio Frequency) 노이즈가 전달되는 경로의 삽입손실을 구하여, 하나의 시험 방법만으로는 넓은 주파수 영역에서 실질적인 IC 전자파 내성시험의 어려움을 발견하였다. 따라서 규정된 시험 방법을 보완하여 넓은 주파수 영역의 노이즈에 대해 신뢰도 높은 IC 전자파 전도내성 시험 방법을 제안한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 C
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• pp.1220-1223
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• 1998

High Power Laboratory is the facility for building to simulate the various phenomena generated from electric systems of the real world and to test making and breaking capability, switching capability and durability of circuit breaker, switchgear and other electric utilities, moreover, load equipments which contain capacitor bank is installed for studying the diverse effects originated from the constituent of load through entire systems or receiving end. Such factors, abnormal voltage or current, can be serious in electrical systems, especially, in the case caused by capacitive components such as overvoltage or inrushcurrent, the problems may be more fatal to the systems. In this paper, the optimal design of capacitor bank which will be equipped in High Power Laboratory, which is for simulating as closely as the practical phenomena resulted from the capacitive currents, and the verification aided by computer simulations are presented. For this, analysis of the circuit characteristics according to the standards which can be criteria of the capacitive current tests and the test circuit configuration in accordance with the analysis are proposed in prelude. In the body of the paper the optimal design of capacitor bank has been obtained on the basis of all conditions mentioned above and the test circuit configuration with LGIS test requirements. furthermore, analysis and verification for the design are derived by EMTP. finally, evaluation for the capacitor bank design and further study plan are concluded.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제54권2호
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• pp.94-100
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• 2005

Korea Electrotechnology Research Institute(KERI) has successfully developed a 100hp-1800rpm-class high temperature superconducting(HTS) motor with high efficiency under partnership with Doosan Heavy Industries & Construction Co. Ltd. This motor has a HTS field winding and an air-cooled stator. The advantages of HTS motor can be represented by a reduction of 50% in both losses and size compared to conventional motors of the same rating. The cooling system is based on the heat transfer mechanism of the thermosyphon by using GM cryocooler as cooling source. The cold head is in contact with the condenser of a Ne-filled thermosyphon. Independently, the rotor assembly was tested at the stationary state and combined with stator. The HTS field winding could be cooled into below 30K. Test of open-circuit characteristics(OCC) and short-circuit characteristics(SCC) and load test with resistive load bank were conducted in generator mode. Also, load tests in motor mode driven by inverter were finished at KERI. Maximum operating current of field winding at 30K was 120A. From OCC and SCC test results synchronous inductance and synchronous reactance were 2.4mH, 0.49pu, respectively. Efficiency of this HTS machine was 93.3% in full load(100hp) test. This paper will present design, construction. and experimental test results of the 100hp HTS machine.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권11호
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• pp.768-775
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• 2004

The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• 한국정보통신학회논문지
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• 제7권4호
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• pp.798-804
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• 2003

본 논문에서는 프린터 head의 노즐분사제어를 위한 개선된 회로를 설계하였다. 기존 방식에 비하여 비하여 Pad 수를 줄임으로서 노즐 수를 확장시킬 수 있다. 제안된 회로는 사전검증을 위하여 먼저 20개의 노즐을 제어하는 sample 회로로 설계하고 FPGA를 이용하여 동작을 확인하였다. 320개의 노즐제어를 위한 전체회로는 sample 회로를 확장하여 ASIC Full Custom 설계방식을 통하여 설계한 뒤 로직 및 회로 simulation 검증을 하였다. 전체회로는 3$\mu\textrm{m}$ CMOS design rule을 적용하여 layout 및 chip으로 제작되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.879-882
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• 2003

Differential Power Analysis(DPA) is powerful attack method for smart card. Self-timed circuit has several advantages resisting to DPA. In that reason, DPA countermeasure using self-timed circuit is thought as one of good solution for DPA prevention. In this paper, we examine what self-timed features are good against DPA, and how much we can get benefit from it. Also we test several self-timed circuit implementation style in order to compare DPA resistance factor. Simulation results show that self-timed circuit is more resistant to DPA than conventional synchronous circuit, and can be used for designing cryptographic hardware for smart-card.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 19-21 Oct. 1992
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• pp.569-572
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• 1992

This paper describes a new method of pseudorandom testing of a digital circuit by use of correlation method and a neural network. The authors have recently proposed a new method of fault diagnosis of logical circuit by applying a pseudorandom M-sequence to the circuit under test, calculating the crosscorrelation function between the input and the output, and comparing the crosscorrelation functions with the references. This method, called MSEC method, is further extended by using a neural network in order to not only detect the existence of faults but also find the place or location of the faults. An experiment by using a simple digital circuit shows enough applicability of this method to industrial testing of circuit board.