• Transactions of the Korean Society of Automotive Engineers
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• v.11 no.5
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• pp.170-175
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• 2003

A control algorithm is developed for highly efficient operation of auxiliary power unit (APU) that consists of a diesel engine and a directly coupled induction generator in series hybrid electric Bus (SHEB). In a series hybrid configuration the APU supplies the electric power needed for maintaining the state of charge (SOC) of the battery unit in various conditions of vehicle operation. As the rotational speed of generator does not depend on the vehicle speed, an optimized operation of engine-generator unit based on the efficiency map of each component can be achieved. The output torque of diesel engine can be controlled by the amount of fuel injection, and the power converted from mechanical to electrical energy can be adjusted by generate control unit (GCU) using the decoupling vector control of torque and flux. As for the given reference of the generating power, the multiply of speed and torque, many combinations of operating speed and torque are possible. The algorithm decides the new operating point based on the engine efficiency map and generator characteristic curve. During the transition of operating points, the speed controller saturation is avoided using variable limit and filtering of generator torque reference. A test rig and SHEB consist of a 1.5L diesel engine and a 30kw induction generator are constructed by Hyundai Motor Company.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.394-396
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• 2006

When developing a new GPS receiver module, the essential problems are evaluation of reliable algorithms, software debugging, and performance comparison between algorithms to find optimal solution. Most GPS receiver modules nowadays use a correlator to track signals from satellites and an MCU (Micro Controller Unit) to control operations of the entire module. The problem of software evaluation from MCU is very difficult, due to limitation of MCU resources and low ability of interfacing with user. Normally, user has to expense special tool kit for a limiting access to MCU but it is also hard to use. This article introduces an implementation of a GPS receiver test bed using correlator GP2021 interfacing with ISA (Industry Standard Architecture) PC bus. This way can give user complete control and visibility into the operation of the receiver, then user can easily debug program and test algorithms. For this article, the least square method is implemented to test the hardware and software performance.

• Publications of The Korean Astronomical Society
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• v.21 no.2
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• pp.67-74
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• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.229-236
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• 2005

This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.255-258
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• 2000

The supplementalγ controls of the FACTS are designed for the enhancement of the small signal stability in power system. The designed supplementary controllers using residue are applied to SVC or TCSC for the improving the damping ratio of dominant eigen value in the New England and 39 bus test system as the sample system. The results show the validation of the supplementary controller for the enhancement of the eigenvalues which have the low frequency oscillations with poor damping ratio as the unstable problem in the sample system.

• Proceedings of the KIEE Conference
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• 2006.11a
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• pp.269-271
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• 2006

In power system, the reactive power is closely associated with voltage. In addition Reactive power has localized characteristic. Recently wide area blackout caused by reactive power imbalance. Therefore it is important to control reactive power considering its characteristic. Until now maintenance of system voltage has been controlled by shunt compensation rather than generators. However because of a large time-constant, shunt compensators are difficult to manage disturbances immediately. In addition shunt compensation has discrete characteristic, which make disturbances in system. In this paper we studied the voltage maintenance method of local buses by controlling the reactive power output of a generator which is closely related a load bus in addition the proposed method was verified by test system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.31-37
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• 1995

In this paper, we propose a programmable 16 bit DSP architecture using FIFO instruction memory. With this DSP architecture, System structure, BUS structure, instruction set ant and an assembler for system test are developed. The characteristic of this structure is that it simply fetches instructions not from RAM but from FIFO using shift operations. Accordingly, System can be designed regardless of RAM access time. One cycle is enough to execute an instruction, if instruction pipeline is operated. Another merit of this structure is that we can obtain the same effect as instruction pipelining without constructing a complex pipelined controller by decreasing the pipeline number.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.98-109
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• 2002

Bluetooth technology is a publicly available specification proposed for Radio Frequency (RF) communication for short-range :1nd point-to-multipoint voice and data transfer. It operates in the 2.4㎓ ISM(Industrial, Scientific and Medical) band and offers the potential for low-cost, broadband wireless access for various mobile and portable devices at range of about 10 meters. In this paper, we describe the structure and the test results of the bluetooth baseband module with direct memory access method we have developed. This module consists of three blocks; link controller, UART interface, and audio CODEC. This module has a bus interface for data communication between this module and main processor and a RF interface for the transmission of bit-stream between this module and RF module. The bus interface includes DMA interface. Compared with the link controller with FIFOs, The module with DMA has a wide difference in size of module and speed of data processing. The small size module supplies lorr cost and various applications. In addition, this supports a firmware upgrade capability through UART. An FPGA and an ASIC implementation of this module, designed as soft If, are tested for file and bit-stream transfers between PCs.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.50-57
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• 2000

By supporting wireless communication technology, there is gradually expansion of the commercial application for Wireless Local Loop(WLL) technology, which is to replace existing telephone line with wireless one. The WLL system application helps a operator to have merits of the installation and maintenance of line and also a subscriber to make a high speed value-added service. As mentioned above reasons for both sides, many manufactories and operators are concerned with development and application respectively. This paper presents hardware implementation of Radio Port Controller(RPC) and also describes the system configuration, functions, and Inter Processor Communication(IPC) structure of RPC. We performed inter-module communication test via IPC backplane bus. And inter-module integration test also completed through data communication and signal waveform measurement repeatedly.