• Title/Summary/Keyword: test bus controller

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Development of Dynamic ID Allocation Algorithm for Real-time Quality-of-Service of Controller Area Network (Controller Area Network 의 실시간 서비스 품질 향상을 위한 동적 ID 할당 알고리즘 개발)

  • Lee, Suk;Ha, Kyoung-Nam;Lee, Kyung-Chang
    • Journal of the Korean Society for Precision Engineering
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    • v.26 no.10
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    • pp.40-46
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    • 2009
  • Recently CAN (Controller Area Network) is widely used as an in-vehicle networking protocol for intelligent vehicle. The identifier field (ID) of CAN is used not only to differentiate the messages but also to give different priorities to access the bus. This paper presents a dynamic 10 allocation algorithm in order to enhance the real-time quality-of-service (QoS) performance. When the network traffic is increased, this algorithm can allocate a network resource to lower priority message without degradation of the real-time QoS performance of higher priority message. In order to demonstrate the algorithm's feasibility, message transmission delays have been measured with and without the algorithm on an experimental network test bed.

Hybrid Fuzzy PI-Control Scheme for Quasi Multi-Pulse Interline Power Flow Controllers Including the P-Q Decoupling Feature

  • Vural, Ahmet Mete;Bayindir, Kamil Cagatay
    • Journal of Power Electronics
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    • v.12 no.5
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    • pp.787-799
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    • 2012
  • Real and reactive power flows on a transmission line interact inherently. This situation degrades power flow controller performance when independent real and reactive power flow regulation is required. In this study, a quasi multi-pulse interline power flow controller (IPFC), consisting of eight six-pulse voltage source converters (VSC) switched at the fundamental frequency is proposed to control real and reactive power flows dynamically on a transmission line in response to a sequence of set-point changes formed by unit-step reference values. It is shown that the proposed hybrid fuzzy-PI commanded IPFC shows better decoupling performance than the parameter optimized PI controllers with analytically calculated feed-forward gains for decoupling. Comparative simulation studies are carried out on a 4-machine 4-bus test power system through a number of case studies. While only the fuzzy inference of the proposed control scheme has been modeled in MATLAB, the power system, converter power circuit, control and calculation blocks have been simulated in PSCAD/EMTDC by interfacing these two packages on-line.

Development of Hardware In-the-Loop Simulation System for Testing Power Management of DC Microgrids Based on Decentralized Control (분산제어 기반 직류 마이크로그리드 전력관리시스템의 HIL 시뮬레이션 적용 연구)

  • To, Dinh-Du;Le, Duc-Dung;Lee, Dong-Choon
    • The Transactions of the Korean Institute of Power Electronics
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    • v.24 no.3
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    • pp.191-200
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    • 2019
  • This study proposes a hardware-in-the-loop simulation (HILS) system based on National Instruments' PXI platform to test power management and operation strategies for DC microgrids (MGs). The HILS system is developed based on the controller HIL prototype, which involves testing the controller board in hardware with a real-time simulation model of the plant in a real-time digital simulator. The system provides an economical and effective testing function for research on MG systems. The decentralized power management strategy based on the DC bus signaling method for DC MGs has been developed and implemented on the HILS platform. HILS results are determined to be similar to those of the off-line simulation in PSIM software.

Automatic Test Case Generation Through 1-to-1 Requirement Modeling (1대1 요구사항 모델링을 통한 테스트 케이스 자동 생성)

  • Oh, Jung-Sup;Choi, Kyung-Hee;Jung, Gi-Hyun
    • The KIPS Transactions:PartD
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    • v.17D no.1
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    • pp.41-52
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    • 2010
  • A relation between generated test cases and an original requirement is important, but it becomes very complex because a relation between requirement models and requirements are m-to-n in automatic test case generation based on models. In this paper, I suggest automatic generation technique for REED (REquirement EDitor), 1-to-1 requirement modeling tool. Test cases are generated though 3 steps, Coverage Target Generation, IORT (Input Output Relation Tree)Generation, and Test Cases Generation. All these steps are running automatically. The generated test cases can be generated from a single requirement. As a result of applying to three real commercial systems, there are 5566 test cases for the Temperature Controller, 3757 test cases for Bus Card Terminal, and 4611 test cases for Excavator Controller.

EXPLORING THE FUEL ECONOMY POTENTIAL OF ISG HYBRID ELECTRIC VEHICLES THROUGH DYNAMIC PROGRAMMING

  • Ao, G.Q.;Qiang, J.X.;Zhong, H.;Yang, L.;Zhuo, B.
    • International Journal of Automotive Technology
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    • v.8 no.6
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    • pp.781-790
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    • 2007
  • Hybrid electric vehicles(HEV) combined with more than one power sources have great potential to improve fuel economy and reduce pollutant emissions. The Integrated Starter Generator(ISG) HEV researched in this paper is a two energy sources vehicle, with a conventional internal combustion engine(ICE) and an energy storage system(batteries). In order to investigate the potential of diesel engine hybrid electric vehicles in fuel economy improvement and emissions reduction, a Dynamic Programming(DP) based supervisory controller is developed to allocate the power requirement between ICE and batteries with the objective of minimizing a weighted cost function over given drive cycles. A fuel-economy-only case and a fuel & emissions case can be achieved by changing specific weighting factors. The simulation results of the fuel-economy-only case show that there is a 45.1% fuel saving potential for this ISG HEV compared to a conventional transit bus. The test results present a 39.6% improvement in fuel economy which validates the simulation results. Compared to the fuel-economy-only case, the fuel & emissions case further reduces the pollutant emissions at a cost of 3.2% and 4.5% of fuel consumption with respect to the simulation and test result respectively.

Development of a Traffic Signal Controller for the Tri-light Traffic Signal (3구신호등 제어용 교통신호제어기 개발)

  • Han, Won-Sub;Gho, Gwang-Yong;Heo, Nak-Won;Lee, Chul-Kee;Ha, Dong-Ik;Lee, Byung-Cheol
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.9 no.5
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    • pp.49-58
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    • 2010
  • The traffic signal controllers being used in the domestic currently are being manufactured based on the korean national police standard which was developed for controlling the quad-light traffic signal having the red, yellow, left-turn arrow, and green lights. But according to the national policy for the traffic operation, they have to be changed to be able to switch the tri-light signal having red, yellow and green lights. In this study, a new tri-light traffic signal controller was designed and developed by the way improving the Signal Control Unit of the existing quad-light standard traffic controller. The Load Signal Unit(LSU) was improved to output 6 signals which are the two assemblies of three signal indications having the red, yellow, and green lights. To enough traffic signals output to control each directional movements and the various transport modes which are car, bus, bike, and pedestrian etc., the connector bus system was designed to be able to accommodate maximum 96 signals outputs being constructed by 16 LSUs. Flasher device was developed to be able to support maximum 32 red signals. In the software, the communication protocol between traffic control center and the traffic signal controller was improved and new signal map code values were defined for the developed LSU controlling the quad-light traffic signal. A model of the quad-light traffic signal controller developed and was tested three operations, protocol-operation, remote-command and control-mode. The test result operated all of them successfully.

An Efficient SoC Test Architecture for Testing Various Cores in Parallel (다양한 코어의 병렬 테스트를 지원하는 효과적인 SOC 테스트 구조)

  • Kim, Hyun-Sik;Kim, Yong-Joon;Park, Hyun-Tae;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.140-150
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    • 2006
  • In this paper, we present a new hardware architecture for testing various cores embedded in SoC. The conventional solutions need much testing time since only one core is tested at single test period. To enhance this, S-TAM, a novel test architecture, and its controller which enable parallel testing of various cores are proposed. S-TAM supports bus sharing to broadcast testing and cores to be tested are selected by using it. In addition, S-TAM controller enables the effective SoC test by simultaneous controlling the various test cores which are based on the different test architectures like IEEE 1149.1 and IEEE 1500.

Design and Implementation of A Test Bus Controller for IEEE 1149.1- Based Test System (IEEE 1149.1을 기반으로 하는 테스트 시스템을 위한 테스트 버스 콘트롤러의 설계 및 구현)

  • 조용태;정득수;송오영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.11B
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    • pp.1948-1956
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    • 2000
  • 본 논문은 보드 레벨 테스팅 및 경계주사기법의 응용을 위한 테스트 버스 콘트롤러의 설계와 구현에 관해 다룬다. 테스트 버스 콘트롤러는 프로세서와 인터페이스를 통하여 IEEE 1149.1 테스트 버스를 제어하기 위한 칩이다. 최근 들어 IEEE 1149.1은 여러 분야에서 응용되어지고 있어서 다양한 응용분야에 적합한 테스트 버스 콘트롤러의 설계가 요구된다. 보드 레벨 테스팅을 위해서 SVF에 정의된 테스트를 수행할 수 있어야 하며, System-on-a-Chip (SoC) 설계 방식에서 내장되어지기 위해서는 작은 칩 크기와 높은 고장 검출률을 가져야 한다. 본 논문에서 구현된 칩은 기존의 테스트 장비에서 널리 쓰이는 SVF에 정의된 테스트를 모두 지원하며, 12k 게이트 정도의 크기를 가진다. 또한 독립적인 칩으로 쓰일 경우는 테스트 버스 콘트롤러가 버스 슬래이브로 쓰일 수 있으므로 IEEE 1149.1 테스트 회로를 가지도록 설계하였다.

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Strategy based PSO for Dynamic Control of UPFC to Enhance Power System Security

  • Mahdad, Belkacem;Bouktir, T.;Srairi, K.
    • Journal of Electrical Engineering and Technology
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    • v.4 no.3
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    • pp.315-322
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    • 2009
  • Penetration and installation of a new dynamic technology known as Flexible AC Transmission Systems (FACTS) in a practical and dynamic network requires and force expert engineer to develop robust and flexible strategy for planning and control. Unified Power Flow Controller (UPFC) is one of the recent and effective FACTS devices designed for multi control operation to enhance the power system security. This paper presents a dynamic strategy based on Particle Swarm Optimization (PSO) for optimal parameters setting of UPFC to enhance the system loadability. Firstly, we perform a multi power flow analysis with load incrementation to construct a global database to determine the initial efficient bounds associated to active power and reactive power target vector. Secondly a PSO technique applied to search the new parameters setting of the UPFC within the initial new active power and reactive power target bounds. The proposed approach is implemented with Matlab program and verified with IEEE 30-Bus test network. The results show that the proposed approach can converge to the near optimum solution with accuracy, and confirm that flexible multi-control of this device coordinated with efficient location enhance the system security of power system by eliminating the overloaded lines and the bus voltage violation.

Design and Implementation of a CAN Data Analysis Test Bench based on Raspberry Pi

  • Pant, Sudarshan;Lee, Sangdon
    • Journal of Multimedia Information System
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    • v.6 no.4
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    • pp.239-244
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    • 2019
  • With the development of Cyber-Physical Systems(CPS), several technologies such as automation control, automotive and intelligent house systems have been developed. To enable communication among various components of such systems, several wired and wireless communication protocols are used. The Controller Area Network(CAN) is one of such wired communication protocols that is popularly used for communication in automobiles and other machinery in the industry. In this paper, we designed and implemented a response time analysis system for CAN communication. The reliable data transfer among various electronic components in a significant time is crucial for the smooth operation of an electric vehicle. Therefore, this system is designed to conveniently analyze the response time of various electronic components of a CAN enabled system. The priority for transmission of the messages in the CAN bus is determined by the message identifier. As the number of nodes increases the transmission of low priority messages is delayed due to the existence of higher priority messages on the bus. We used Raspberry Pi3 and PiCAN2 board to simulate the data transfer for studying the comparative delay in low priority nodes.