• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.74-79
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• 2006

Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-Chip (SoC) adopting Advanced Microcontroller Bus Architecture (AMBA) bus system. Accordingly, this architecture has a deficiency of not being able to concurrently shifting in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. While preserving the compatability with the ARM TIC, since scan in and out operations can be performed simultaneously, test application time through the expensive Automatic Test Equipment (ATE) can be drastically reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.54-60
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• 2006

In order to test the board with IEEE 1149.1 boundary scan design, the test sequence must be applied as the bit stream However it is very tedious job to generate the test bit sequence since it requires the complete hlowledge about the 1149.1. This fuper introduces a convenient PCI/USB interface controller, named as Test-Ready PCI (TRPCI) ard Test-Ready USB (TRUSB). Test Bus Controller has been developed by TI and Lucent aiming to generate the test bit stream as an instruction level, thus even the novice test engineer can easily generate the test sequence.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.54-60
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• 2008

The bus architecture consists of a master initiating a communication transaction, a slave responding to the transaction, a arbiter selecting a master, a bridge connecting buses and so on. Recently this is more complicated and developed toward multi-bus architecture. In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory selector is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.9
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• pp.825-832
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• 2016

This paper describes the development of a data bus analyzer for use in avionics systems integration test. The data bus analyzer is equipped with MIL-STD-1553B, CAN and Ethernet interface cards which is incorporated in a majority of the avionics systems to accommodate a variety of interfaces. It has an individual hardware for a capture engine and a analyzing engine in order to perform the collection and the analysis of the bus data at the same time efficiently. It provides a data display function of the grid, 2-dimensional and 3-dimensional form to increase the data analysis efficiency. Verification of the data bus analyzer was carried out module unit testing and inter-module integration testing on the basis of the test procedures. Verification of interlocking requirement and usefulness of developed equipment was confirmed through an integration test result performed on a system integration laboratory of aircraft which is an actual testing environment.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.649-656
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• 2007

Today, controller area network(CAN) is a field bus that is nowadays widespread in distributed embedded systems due to its electrical robustness, low price, and deterministic access delay. However, its use safety-critical applications has been controversial due to dependability limitation, such as those arising from its bus topology. Thus it is important to analyze the performance of the network in terms of load of data bus, maximum time delay, communication contention, and others during the design phase of the controller area network. In this paper, a simulation algorithm is introduced to evaluate the communication performance of the vehicle network and apply software base fault injection techniques. This can not only reduce any erratic implementation of the vehicle network but it also improves the reliability of the system.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.527-528
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• 2008

In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory decoder is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.523-530
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• 2005

When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann't fully improve performance because a target device doesn't know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don't know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about $9\%$.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.4
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• pp.263-270
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• 2021

Active AC/DC converters with PWM operation are utilized to regulate rectified DC bus voltage of a permanent magnet synchronous generator in the maritime DC power system. A DC bus voltage regulation strategy that exploits the six-step operation is proposed in this study. Compared with that of the PWM operation, switching loss of the converter can be significantly reduced under the six-step operation. Moreover, conduction loss can also be reduced due to the high modulation index and reduced flux-weakening current of the six-step operation. A controller is used for the proposed DC bus voltage regulation strategy to verify its validity with the simulation and experimental setup. The simulation and the experimental test results showed that the converter loss reduces to a maximum of 70% and 19%, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.2
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• pp.71-76
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• 2016

A controller area network (CAN) receiver measures differential voltage on a bus to determine the bus level. Since 3.3V transceivers generate the same differential voltage as 5V transceivers (usually ${\geq}1.5V$), all transceivers on the bus (regardless of supply voltage) can decipher the message. In fact, the other transceivers cannot even determine or show that there is anything different about the differential voltage levels. A new CMOS RC oscillator insensitive supply voltage for clock generation in a CAN transceiver was fabricated and tested to compensate for this drawback in CAN communication. The system consists of a symmetrical circuit for voltage and current switches, two capacitors, two comparators, and an RS flip-flop. The operational principle is similar to a bistable multivibrator but the oscillation frequency can also be controlled via a bias current and reference voltage. The chip test experimental results show that oscillation frequency and power dissipation are 500 kHz and 5.48 mW, respectively at a supply voltage of 3.3 V. The chip, chip area is $0.021mm^2$, is fabricated with $0.18{\mu}m$ CMOS technology from SK hynix.