Implementation of AHB1-AHB2 Multi-Bus Architecture Using Memory Selector

메모리 셀렉터를 이용한 AHB1-AHB2 다중버스 아키텍처 구조 구현

In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory decoder is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.