• Title/Summary/Keyword: test algorithm

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Guided Missile Assembly Test Set using Encryption AES Rijndael Algorithm (암호화 AES Rijndael 알고리즘 적용 유도탄 점검 장비)

  • Jung, Eui-Jae;Koh, Sang-Hoon;Lee, You-Sang;Kim, Young-Sung
    • Journal of Advanced Navigation Technology
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    • v.23 no.5
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    • pp.339-344
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    • 2019
  • In order to prepare for the rise of data security threats caused by the information and communication technology, technology that can guarantee the stability of the data stored in the missile test set is important. For this purpose, encryption should be performed when data is stored so that it cannot be restored even if data is leaked, and integrity should be ensured even after decrypting the data. In this paper, we apply AES algorithm, which is a symmetric key cryptography system, to the missile test set, and Encrypt and decrypt according to the amount of data for each bit of each AES algorithm. We implemented the AES Rijndael algorithm in the existing inspection system to analyze the effect of encryption and apply the proposed encryption algorithm to the existing system. confirmation of suitability. analysis of capacity and Algorithm bits it is confirmed that the proposed algorithm will not affect the system operation and the optimal algorithm is derived. compared with the initial data, we can confirm that the algorithm can guarantee data undulation.

Performance Comparison of Semi-active Control Algorithms for a Large-scale MR Damper using Real-time Hybrid Test Method (실시간 하이브리드 실험법을 이용한 대형 MR감쇠기의 준능동 제어알고리즘 성능 비교)

  • Park, Eun-Churn;Lee, Sung-Kyung;Lee, Heon-Jae;Choi, Kang-Min;Moon, Suk-Jun;Jung, Hyung-Jo;Chung, Hee-San;Min, Kyung-Won
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2007.11a
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    • pp.648-654
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    • 2007
  • This paper presents the result of a comparison study to evaluate the performance of several semi-active control algorithms for use with large-scale MR damper applied to a building structure under seismic excitation using real-time hybrid test method. Recently, a variety of semi-active control algorithm studies are developed and generally evaluated the performance by using numerical analysis. In this paper real-time hybrid test method was applied to performance evaluating of semi-active control algorithms including a clipped optimal algorithm and the modulated homogeneous friction algorithm.

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Development of the Algorithm for Discriminating Faults from Variation using Wavelet Transform (웨이블릿 변환을 이용한 고장과 Variation의 유형 구분 알고리즘 개발)

  • Seo, Hun-Chul;Lee, Soon-Jeong;Kim, Chul-Hwan
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.8
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    • pp.1460-1466
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    • 2011
  • This paper proposes the algorithm for discriminating faults from the variation due to the operation of non-linear components to prevent the mal-operation of protection relay in the distribution system. An IEEE 13 node test feeder is modeled to analyze the characteristics of the fault and each variation using EMTP-RV. Simulations with various operating conditions of transformers, non-linear loads, and unbalanced loads are performed using the test feeder model. Based on simulation results, the wavelet transform is adopted to analyze the current waveforms from the faults and variations to find out the differences between them and the algorithm for discriminating faults from the variation is proposed. The proposed algorithm is verified by using the current waveforms simulated in the KEPCO's distiribution system and IEEE 13 node test feeder.

A Study on Data Clustering Method Using Local Probability (국부 확률을 이용한 데이터 분류에 관한 연구)

  • Son, Chang-Ho;Choi, Won-Ho;Lee, Jae-Kook
    • Journal of Institute of Control, Robotics and Systems
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    • v.13 no.1
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    • pp.46-51
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    • 2007
  • In this paper, we propose a new data clustering method using local probability and hypothesis theory. To cluster the test data set we analyze the local area of the test data set using local probability distribution and decide the candidate class of the data set using mean standard deviation and variance etc. To decide each class of the test data, statistical hypothesis theory is applied to the decided candidate class of the test data set. For evaluating, the proposed classification method is compared to the conventional fuzzy c-mean method, k-means algorithm and Discriminator analysis algorithm. The simulation results show more accuracy than results of fuzzy c-mean method, k-means algorithm and Discriminator analysis algorithm.

Implementation of a Real-time Data fusion Algorithm for Flight Test Computer (비행시험통제컴퓨터용 실시간 데이터 융합 알고리듬의 구현)

  • Lee, Yong-Jae;Won, Jong-Hoon;Lee, Ja-Sung
    • Journal of the Korea Institute of Military Science and Technology
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    • v.8 no.4 s.23
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    • pp.24-31
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    • 2005
  • This paper presents an implementation of a real-time multi-sensor data fusion algorithm for Flight Test Computer. The sensor data consist of positional information of the target from a radar, a GPS receiver and an INS. The data fusion algorithm is designed by the 21st order distributed Kalman Filter which is based on the PVA model with sensor bias states. A fault detection and correction logics are included in the algorithm for bad measurements and sensor faults. The statistical parameters for the states are obtained from Monte Carlo simulations and covariance analysis using test tracking data. The designed filter is verified by using real data both in post processing and real-time processing.

A New Test Algorithm for Effective Interconnect Testing Among SoC IPs (SoC IP 간의 효과적인 연결 테스트를 위한 알고리듬 개발)

  • 김용준;강성호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.1
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    • pp.61-71
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    • 2003
  • Interconnect test for highly integrated environments like SoC, becomes more important as the complexity of a circuit increases. This importance is from two facts, test time and complete diagnosis. Since the interconnect test between IPs is based on the scan technology such as IEEE1149.1 and IEEE P1500, it takes long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue because a defect on interconnects are shown as a defect on a chip. But generally, interconnect test algorithms that need the short test time can not do complete diagnosis and algorithms that perform complete diagnosis need long test time. A new interconnect test algorithm is developed. The new algorithm can provide a complete diagnosis for all faults with shorter test length compared to the previous algorithms.

A New Test Algorithm for High-Density Memories (고집적 메모리를 위한 새로운 테스트 알고리즘)

  • Kang, Dong-Chual;Cho, Sang-Bock
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.59-62
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    • 2000
  • As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. From now on, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new algorithm for NPSFs, and neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. To consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e., write \longrightarrow refresh \longrightarrow read). Also, we present properties of the algorithm, such as its capability to detect stuck-at faults, transition faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

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ICAIM;An Improved CAIM Algorithm for Knowledge Discovery

  • Yaowapanee, Piriya;Pinngern, Ouen
    • 제어로봇시스템학회:학술대회논문집
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    • 2004.08a
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    • pp.2029-2032
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    • 2004
  • The quantity of data were rapidly increased recently and caused the data overwhelming. This led to be difficult in searching the required data. The method of eliminating redundant data was needed. One of the efficient methods was Knowledge Discovery in Database (KDD). Generally data can be separate into 2 cases, continuous data and discrete data. This paper describes algorithm that transforms continuous attributes into discrete ones. We present an Improved Class Attribute Interdependence Maximization (ICAIM), which designed to work with supervised data, for discretized process. The algorithm does not require user to predefine the number of intervals. ICAIM improved CAIM by using significant test to determine which interval should be merged to one interval. Our goal is to generate a minimal number of discrete intervals and improve accuracy for classified class. We used iris plant dataset (IRIS) to test this algorithm compare with CAIM algorithm.

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Algorithms for Detecting Coupling Faults in Semiconductor RAM's (반도체 RAM의 결합고장을 검출하는 알고리듬)

  • 여정모;조상복
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.1
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    • pp.51-63
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    • 1993
  • "Algorithm DA" is proposed to test linked 2-CFs(2-Coupling Faults) with order 2 or 3 which are not perfectly detected in conventional algorithms. "Test 1*", "Test 2*" and "Algorithm RA" are proposed restricted 3-CFS. The time complexity of "Test 1*" is reduced in view of the detection of 3-CFS. "Test 2*" and "Algorithm RA" have not only the reduces time complexity but also the improved fault coverage in comparison with conventional algorithms. And "Algorithm RA" can be applied step by step according to the degree of the fault coverage. If "Algorithm RA" is applied to the memory with parallel test. its time complexity is reduced considerably. It is proved that the MT(March Test) with nonlinear address sequences can not detect perfectly the CFs more complex than linked 2-CFs with order 3.ss sequences can not detect perfectly the CFs more complex than linked 2-CFs with order 3.

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A new efficient algorithm for test pattern compression considering low power test in SoC (SoC환경에서의 저전력 테스트를 고려한 테스트 패턴 압축에 대한 효율적인 알고리즘)

  • 신용승;강성호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.9
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    • pp.85-95
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    • 2004
  • As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.