• Title/Summary/Keyword: test Si wafer

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Fabrication and Reliability Test of Device Embedded Flexible Module (디바이스 내장형 플렉시블 전자 모듈 제조 및 신뢰성 평가)

  • Kim, Dae Gon;Hong, Sung Taik;Kim, Deok Heung;Hong, Won Sik;Lee, Chang-Woo
    • Journal of Welding and Joining
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    • v.31 no.3
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    • pp.84-88
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    • 2013
  • These days embedded technology may be the most significant development in the electronics industry. The study focused on the development of active device embedding using flexible printed circuit in view of process and materials. The authors fabricated 30um thickness Si chip without any crack, chipping defects with a dicing before grinding process. In order to embed chips into flexible PCB, the chip pads on a chip are connected to bonding pad on flexible PCB using an ACF film. After packaging, all sample were tested by the O/S test and carried out the reliability test. All samples passed environmental reliability test. In the future, this technology will be applied to the wearable electronics and flexible display in the variety of electronics product.

High-speed Performance of Single Flux Quantum Circuits Test Probe (단자속 양자 회로 측정용 고속 프로브의 성능 시험)

  • 김상문;최종현;김영환;강준희;윤기현;최인훈
    • Progress in Superconductivity
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    • v.4 no.1
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    • pp.74-79
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    • 2002
  • High-speed probe made to test single flux quantum(SFQ) circuits was comprised of semi-rigid coaxial cables and microstrip lines. The impedance was set at 50 $\Omega$to carry high-speed signals without much loss. To do performance test of high-speed probe, we have attempted to fabricate a test chip which has a coplanar waveguide(CPW) structure. Electromagnetic simulation was done to optimize the dimension of CPW so that the CPW structure has an impedance of 50$\Omega$, matching in impedance with the probe. We also used the simulation to investigate the effect of the width of signal line and the gap between signal line and ground plane to the characteristics of CPW structure. We fabricated the CPW structure with a gold film deposited on Si wafer whose resistivity was above $1.5\times$10$_4$$\Omega$.cm. The magnitudes of S/sub 21/ of CPW at 6 ㎓ in simulations and in the actual measurements done with a network analyzer were: -0.1 ㏈ and -0.33 ㏈ (type A),-0.2 ㏈ and -0.48 ㏈ (type B), respectively. Using the test chip, we have successfully tested the performance of high-speed probe made for SFQ circuits. The probe showed the good performance overthe bandwidth of 10 ㎓.

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Study on Frictional Characteristics of Sub-micro Structured Silicon Surfaces (서브 마이크로 구조를 가진 실리콘 표면의 마찰 특성 연구)

  • Han, Ji-Hee;Han, Gue-Bum;Jang, Dong-Yong;Ahn, Hyo-Sok
    • Tribology and Lubricants
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    • v.33 no.3
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    • pp.92-97
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    • 2017
  • The understanding of the friction characteristics of micro-textured surface is of great importance to enhance the tribological properties of nano- and micro-devices. We fabricate rectangular patterns with submicron-scale structures on a Si wafer surface with various pitches and heights by using a focused ion beam (FIB). In addition, we fabricate tilted rectangular patterns to identify the influence of the tilt angle ($45^{\circ}$ and $135^{\circ}$) on friction behaviour. We perform the friction test using lateral force microscopy (LFM) employing a colloidal probe. We fabricate the colloidal probe by attaching a $10{\pm}1-{\mu}m$-diameter borosilicate glass sphere to a tipless silicon cantilever by using a ultraviolet cure adhesive. The applied normal loads range between 200 nN and 1100 nN and the sliding speed was set to $12{\mu}m/s$. The test results show that the friction behavior varied depending on the pitch, height, and tilt angle of the microstructure. The friction forces were relatively lower for narrower and deeper pitches. The comparison of friction force between the sub-micro-structured surfaces and the original Si surface indicate an improvement of the friction property at a low load range. The current study provides a better understanding of the influence of pitch, height, and tilt angle of the microstructure on their tribological properties, enabling the design of sub-micro- and micro-structured Si surfaces to improve their mechanical durability.

High-Efficiency a-Si:H Solar Cell Using In-Situ Plasma Treatment

  • Han, Seung Hee;Moon, Sun-Woo;Kim, Kyunghun;Kim, Sung Min;Jang, Jinhyeok;Lee, Seungmin;Kim, Jungsu
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.230-230
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    • 2013
  • In amorphous or microcrystalline thin-film silicon solar cells, p-i-n structure is used instead of p/n junction structure as in wafer-based Si solar cells. Hence, these p-i-n structured solar cells inevitably consist of many interfaces and the cell efficiency critically depends on the effective control of these interfaces. In this study, in-situ plasma treatment process of the interfaces was developed to improve the efficiency of a-Si:H solar cell. The p-i-n cell was deposited using a single-chamber VHF-PECVD system, which was driven by a pulsed-RF generator at 80 MHz. In order to solve the cross-contamination problem of p-i layer, high RF power was applied without supplying SiH4 gas after p-layer deposition, which effectively cleaned B contamination inside chamber wall from p-layer deposition. In addition to the p-i interface control, various interface control techniques such as thin layer of TiO2 deposition to prevent H2 plasma reduction of FTO layer, multiple applications of thin i-layer deposition and H2 plasma treatment, H2 plasma treatment of i-layer prior to n-layer deposition, etc. were developed. In order to reduce the reflection at the air-glass interface, anti-reflective SiO2 coating was also adopted. The initial solar cell efficiency over 11% could be achieved for test cell area of 0.2 $cm^2$.

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Evaluation of Micro-Tensile Properties for Nano-coating Material TiN (나노 코팅재 TiN 의 마이크로 인장 특성 평가)

  • Huh, Yong-Hak;Kim, Dong-Iel;Hahn, Jun-Hee;Kim, Gwang-Seok;Yeon, Soon-Chang;Kim, Yong-Hyub
    • Proceedings of the KSME Conference
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    • 2004.04a
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    • pp.240-245
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    • 2004
  • Tensile properties of hard coating material, TiN, were evaluated using micro-tensile testing system. TiN has been known as a hard coating material commonly used today. Micro-tensile testing system consisted of a micro tensile loading system and a micro-ESPI(Electronic Speckle Pattern Interferometry) system. Micro-tensile loading system had a maximum load capacity of 500mN and a resolution of 4.5 nm in stroke. TiN thin film $1{\mu}m$ thick was deposited on the Si wafer pre-deposited of $Si_3N_4$ film substrate by the closed field unbalanced magnetron sputtering (CFUBMS) process. Three kinds of micro-tensile specimen with the respective width of $50{\mu}m$, $100{\mu}m$ and $500{\mu}m$ were fabricated by MEMS process. The mechanical properties including tensile strength and elastic modulus were determined using the micro-tensile testing system and compared by those obtained by nano-indentation

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Application of Laser Interferometry for Assessment of Surface Residual Stress by Determination of Stress-free State (무잔류 응력상태 결정을 통한 표면 잔류응력장 평가에의 레이저 간섭계 적용)

  • 김동원;이낙규;나경환;권동일
    • Journal of the Semiconductor & Display Technology
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    • v.3 no.2
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    • pp.35-40
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    • 2004
  • The total relaxed stress in annealing and the thermal strain/stress were obtained from the identification of the residual stress-free state using electronic speckle pattern interferometry (ESPI). The residual stress fields in case of both single and film / substrate systems were modeled using the thermo-elastic theory and the relationship between relaxed stresses and displacements. We mapped the surface residual stress fields on the indented bulk Cu and the 0.5 $\mu\textrm{m}$ Au film by ESPI. In indented Cu, the normal and shear residual stress are distributed over -1.7 GPa to 700 MPa and -800 GPa to 600 MPa respectively around the indented point and in deposited Au film on Si wafer, the tensile residual stress is uniformly distributed on the Au film from 500 MPa to 800 MPa. Also we measured the residual stress by the x-ray diffractometer (XRD) for the verification of above residual stress results by ESPI...

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Tribological Properties of DLC film on Modified Surface by TiC Plasma Immersion Ion Implantation and Deposition (TiC 이온 주입 층에 증착된 DLC 박막의 트라이볼로지적 특성)

  • Yi, Jin-Woo;Kim, Jong-Kuk;Kim, Seock-Sam
    • Proceedings of the KSME Conference
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    • 2004.04a
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    • pp.956-960
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    • 2004
  • Effects of ion implantation and deposition on the tribological properties of DLC film as a function of implanted energies and process times were investigated. TiC ions were implanted and deposited on the Si-wafer substrates followed by DLC coating using ion beam deposition method. In order to study tribological properties such as friction coefficient and behavior of DLC film on the modified surface as a function of implanted energies and process times, we used a ball-on-disc type apparatus in the atmospheric environment. From results of wear test, as the implanted energy was increased, the friction coefficient was more stable below 0.1.

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Design, Fabrication, and Testing of a MEMS Microturbine

  • Jeon Byung Sun;Park Kun Joong;Song Seung Jin;Joo Young Chang;Min Kyoung Doug
    • Journal of Mechanical Science and Technology
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    • v.19 no.2
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    • pp.682-691
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    • 2005
  • This paper describes the design, fabrication, and testing of a microturbine developed at Seoul National University. Here, the term 'microturbine' refers to a radial turbine with a diameter on the order of a centimeter. Such devices can be used to transmit power for various systems. The turbine is designed using a commercial CFD code, and it has a design flow coefficient of 0.238 and work coefficient of 0.542. It has 31 stator blades and 24 rotor blades. A hydrodynamic journal bearing and hydrostatic thrust bearings counteract radial and axial forces on the rotor. The test turbine consists of a stack of five wafers and is fabricated by MEMS technology, using photolithography, DRIE, and bonding processes. The first, second, fourth, and fifth layers contain plumbing, and hydrostatic axial thrust bearings for the turbine. The third wafer contains the turbine's stator, rotor, and hydrodynamic journal bearings. Furthermore, a turbine test facility containing a flow control system and instrumentation has been designed and constructed. In performance tests, a maximum rotation speed of 11,400 rpm and flow rate of 16,000 sccm have been achieved.

Dislocations as native nanostructures - electronic properties

  • Reiche, Manfred;Kittler, Martin;Uebensee, Hartmut;Pippel, Eckhard;Hopfe, Sigrid
    • Advances in nano research
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    • v.2 no.1
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    • pp.1-14
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    • 2014
  • Dislocations are basic crystal defects and represent one-dimensional native nanostructures embedded in a perfect crystalline matrix. Their structure is predefined by crystal symmetry. Two-dimensional, self-organized arrays of such nanostructures are realized reproducibly using specific preparation conditions (semiconductor wafer direct bonding). This technique allows separating dislocations up to a few hundred nanometers which enables electrical measurements of only a few, or, in the ideal case, of an individual dislocation. Electrical properties of dislocations in silicon were measured using MOSFETs as test structures. It is shown that an increase of the drain current results for nMOSFETs which is caused by a high concentration of electrons on dislocations in p-type material. The number of electrons on a dislocation is estimated from device simulations. This leads to the conclusion that metallic-like conduction exists along dislocations in this material caused by a one-dimensional carrier confinement. On the other hand, measurements of pMOSFETs prepared in n-type silicon proved the dominant transport of holes along dislocations. The experimentally measured increase of the drain current, however, is here not only caused by an higher hole concentration on these defects but also by an increasing hole mobility along dislocations. All the data proved for the first time the ambipolar behavior of dislocations in silicon. Dislocations in p-type Si form efficient one-dimensional channels for electrons, while dislocations in n-type material cause one-dimensional channels for holes.

Chemical Vapor Deposition of Tungsten by Silane Reduction (사일린 환원반응에 의한 텅스텐 박막의 화학증착)

  • Hwang, Sung-Bo;Choi, Kyeong-Keun;Rhee Shi-Woo
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.10
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    • pp.113-123
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    • 1990
  • Tungsten film was deposited on the single crystal silicon wafer in a low pressure chemical vapor deposition reactor from silane and tungsten hexafluoride in the temperature range of $250-400^{\circ}C$ Deposition rate was found to be determined by the mass transfer rate of reactants from the gas phase to the safter surface. It was found out that tungsten films deposited contained about 3 atomic $\%$ of silicon and that the crystallinity and the grain size increased as the deposition temperature was increased. The resistivity of the film was measured to be in the range of $7~25{\mu}{\Omega}-cm$ and decreased with increasing deposition temperature. The adhesion of the tungsten film on a silicon surface was measured by the tape peel off test and it was improved with increasing deposition temperature. From the analysis of the gas composition, the reaction pathway to form $SiF_{4}$ and $H_{2}$ was found to be more favorable than HF formation.

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