• Kyungpook Mathematical Journal
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• v.62 no.1
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• pp.57-67
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• 2022

In the present study, we introduce a valuation of ternary semiring on an ordered abelian group. Motivated by the construction of valuation rings, we study some properties of ideals in ternary semiring arising in connection with the valuation map. We also explore ternary valuation semirings for a noncommuative ternary division semiring. We further consider the notion of convexity in a ternary semiring and how it is reflected in the valuation map.

• Communications of the Korean Mathematical Society
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• v.23 no.3
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• pp.387-399
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• 2008

We investigate approximately higher ternary derivations in Banach ternary algebras via the Cauchy functional equation $$f({\lambda}_{1x}+{\lambda}_{2y}+{\lambda}_{3z}={\lambda}_1f(x)+{\lambda}_2f(y)+{\lambda}_3f(z)$$.

• Journal of the Chungcheong Mathematical Society
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• v.20 no.3
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• pp.191-201
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• 2007

In this paper we introduce the notion of congruence on a ternary semigroup and study some interesting properties. We also introduce the notions of cancellative congruence, group congruence and Rees congruence and characterize these congruences in ternary semigroups.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.134-138
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• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• Kyungpook Mathematical Journal
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• v.55 no.4
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• pp.893-907
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• 2015

The Hyers-Ulam-Rassias stability of the k-th partial ternary quadratic derivations is investigated in non-Archimedean Banach ternary algebras and non-Archimedean $C^*$-ternary algebras by using the fixed point theorem.

• The Pure and Applied Mathematics
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• v.22 no.4
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• pp.383-387
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• 2015

In [1], the definition of C*-Lie ternary (σ,τ,ξ)-derivation is not well-defined and so the results of [1, Section 4] on C*-Lie ternary (σ,τ,ξ)-derivations should be corrected.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.142-144
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• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.47-53
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• 2004

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are composed with ternary voltage mode NMAX, NMIN, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.35um CMOS technology and 3.3Volts supply voltage. The architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• Journal of the Korean Mathematical Society
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• v.46 no.4
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• pp.775-784
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• 2009

In 1932, Lehmer [4] gave the definition of a ternary semigroup. We can see that any semigroup can be reduced to a ternary semigroup. In this paper, we give some auxiliary results which are also necessary for our considerations and characterize the relationship between the (0-)minimal and maximal ordered lateral ideals and the lateral simple and lateral 0-simple ordered ternary semigroups analogous to the characterizations of minimal and maximal left ideals in ordered semigroups considered by Cao and Xu [2].

• Kyungpook Mathematical Journal
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• v.52 no.4
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• pp.375-381
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• 2012

We introduce the concepts of ordered quasi-ideals, ordered bi-ideals in an ordered ternary semigroup and study their properties. Also regular ordered ternary semigroup is defined and several ideal-theoretical characterizations of the regular ordered ternary semigroups are furnished.