• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.263-266
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• 2005

An UHF ($860{\sim}960MHz$) RFID tag antenna is optimized and designed using a genetic algorithm (GA). The tag antenna impedance should be matched to the conjugate of the impedance of the tag IC Chip. The chip impedance has real and capacitive imaginary parts due to the parasitic capacitance of the RFID chip. A GA linked with a commercially available antenna simulation program optimizes the UHF $860{\sim}960\;MHz$ tag antenna to match a commercially available RFID chip. This method shows that any RFID antenna can be designed for any commercial RFID chip with any impedance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.12
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• pp.1228-1235
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• 2014

Input impedance of UHF RFID tag chip is needed to design a tag. In determining the chip impedance, direct measurement method is adopted commonly. In this paper, problems generated from fixtures that interface between tag chip and coaxial-oriented measurement instrument are investigated and the result of the problems is shown, when the direct measurement method is applied. As an alternative to the method, a modeling method is proposed and its validity and accuracy are shown.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.203-211
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• 2013

UHF RFID tag designers usually ndde the chip impedance and read power sensitivity value obtained when a tag chip is mounted on a chip pad. The chip impedance, however, is not able to be supplied by chip manufacturer, since the chip impedance is varied according to tag designs and fabrication processes. Instead, the chip makers mostly supply the chip impedances measured on the bare dies. This study proposes a chip impedance and read power sensitivity evaluation method which requires a few simple auxiliary and some RF measuring equipment. As it is impractical to measure the chip impedance directly at mounted chip terminals, some form test fixture is employed and the effect of the fixture is modeled and de-embeded to determine the chip impedance and the read power sensitivity. Validity and accuracy of the proposed de-embed method are examined by using commercial RFID tag chips as well as a capacitor and a resistor the value of which are known.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1B
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• pp.62-67
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• 2010

Our research group has investigated that RFID tag packaging development and RFID tag flip chip bonding method influences on the industry-environmental customized RFID tag development that has applications to various industry environmental conditions. RFID tag flip chip bonding is consisting with wire bonding, ultrasonic bonding, heat plate bonding, and laser bonding and those methods are also depending on the different RFID tag development. Our research data shows that, among the various industrial environments such as an extremely high temperature, cryogenic, high-humidity, flexible, high-durable, development of RFID tag in an extremely high temperature is inappropriate for laser bonding method, converting of heat energy as absorbing light energy or heat plate bonding method of straight heat transferring manner, on the other hand, is suitable for wire bonding method which directly connect bump to pattern using wire.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.8 s.99
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• pp.797-802
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• 2005

In this paper, we design a UHF band RFID tag antenna which is conjugate matched to an impedance of a chip and also mountable on conductive materials. The proposed tag antenna is very compact($50{\times}30{\times}4mm$) with a modified PIFA shape. The proposed tag antenna has an advantage of easy matching to various chip input impedances. The performance of the antenna is evaluated by monitoring RCS in the reader direction. The RCS of the designed tag is $-10.2\;dBm^2$ when the chip is shorted and is $-21\;dBm^2$ when the chip impedance is a complex conjugate of the antenna impedance.

• ETRI Journal
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• v.30 no.3
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• pp.347-354
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• 2008

In this paper, the design of a low-power 512-bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low-power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage-up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 ${\mu}m$ EEPROM process. Power dissipation is 32.78 ${\mu}W$ in the read cycle and 78.05 ${\mu}W$ in the write cycle. The layout size is 449.3 ${\mu}m$ ${\times}$ 480.67 ${\mu}m$.

• Journal of Korea Multimedia Society
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• v.14 no.2
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• pp.194-200
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• 2011

Recently, RFID(Radio Frequency IDentification) market spread in industry region is entering a phase of stagnation due to cost issue. RFID tag inlay cost has become relatively more expensive due to the recent decrease in chip price. Therefore, a simple and rapid design technique for RFID tag has yet to be implemented to achieve low cost. This paper presents a design technique considering chip impedance for antenna design for improved accuracy and computation time. As a result, it is confirmed that analysis error for resonance ranges within 20MHz and readable range error falls within 1.5m.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.469-472
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• 2008

In this paper, we discuss the recent trends on the passive UHF RFID tag chip design techniques and several important system parameters. We also summarize link budget studies on both conventional and modem UHF RFID communications. The paper highlights the reverse link limited case, which has known to be the minor concern if reader continuous wave (CW) can reach the tag in sufficient level. This makes sense when the tag sensitivity is rather high (over 10-12${\mu}W$); however, since the tag chip fabrication technologies have been developed by time, the tag chip threshold levels are now less-dominant in determining link margin. If the tag limitation can be alleviated, the forward link limited case can be resolved; thus, we rather focus on the path-loss problem. Since the path-losses are still exist in both forward and reverse links, and it can be doubled while CW travels the reader-tag-reader path because forward link and reverse link are on the same distance. Consider if reader receiver sensitivity is very high in the worst case. In this case, weaken tag response (i.e., backscatters) cannot reach the level that reader receiver can process tag data; bit-error rate can be higher. Overall, backscatter levels should be high enough so that reader receiver can correctly function. After discussing link budget, we carried out practical measurements on fading effects between two circularly polarized UHF RFID antennas in a small scale area.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.279-284
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• 2005

We investigated the impedance matching characteristics of UHF-band RFID tag antenna and tag chip for increased reading range. A voltage multiplier designed using 0.4 $\mu$m zero-$V_T$ MOSFET showed that DC output voltage of about 2 V can be obtained using standard CMOS process. The input impedance of the voltage multiplier was examined to achieve impedance matching to the RFID tag antenna using analytical and numerical approaches. The input impedance of the voltage multiplier could be varied in a wide range by selecting the size of MOSFET and the number of multiplying stages, and thus can be impedance matched to a tag antenna in presence of other tag circuit blocks. A meander line inductively-coupled RFID tag antenna operating at UHF band also shows the feasibility of impedance matching to tile RFID tag chip.

• Journal of Navigation and Port Research
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• v.32 no.5
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• pp.363-368
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• 2008

This paper presents a miniaturization design technique of radio frequency identification (RFID) tag antenna operated in 910 MHz band. Miniaturization structure design for a tag antenna is performed by structure application of the folded dipole and meander line. In order to realize the maximum power transmission, imaginary part of a chip impedance and a tag antenna impedance is matched by complex conjugate number. The optimized tag antenna size is $50\;nm\;{\times}\;40\;nm\;{\times}\;1.6\;nm$ and its size is reduced about 62 % comparison with antenna size of reference [4]. The measured results of fabricated tag antenna are confirmed the reasonable agreement with prediction. The read range of the tag antenna with chip observed about 5 m.