• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2002.06a
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• pp.87-87
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• 2002

본 논문에서는 모듈성과 확장성을 갖는 시스톨릭 어레이 정렬기(Systolic Array Sorter)의 구현에 대하여 기술한다. 정규순환방정식으로 표현된 정렬(sorting)알고리즘으로부터 1차원 평면 시스톨릭 어레이를 유도한 후 유도된 정렬 시스톨릭 어레이를 RTL 수준에서 VHDL로 모델링 하여 동작을 검증하였다. 검증된 시스톨릭 어레이 정렬기는 synopsys hynix-0.35$\mu\textrm{m}$ 셀 라이브러리와 FPGA s40pq240칩을 사용하여 합성 및 구현되었다.

• Journal of the Korea Computer Industry Society
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• v.5 no.4
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• pp.511-516
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• 2004

In this paper, we propose a low-power motion-estimation VLSI architecture based on systolic array using partial norms and spatial correlation. Our approach reduces computational load based on eliminating invalid block-matching points.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.277-280
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• 2002

This paper analyze the characteristics of three multipliers in finite fields GF(2m) from the point of view of processing time and area complexity. First, we analyze structure of three multipliers; 1) LSB-first systolic array, 2) LFSR structure, and 3) CA structure. To make performance analysis, each multiplier was modeled in VHDL and was synthesized for FPGA implementation. The simulation results show that LFSR structure is best from the point of view of area complexity, and LSB systolic array is best from the point of view of processing time per clock.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.44-50
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• 1993

In this paper, we will present an array processor for implementation of digital neural networks. Back-propagation model can be formulated as a consecutive matrix-vector multiplication problem with some prespecified thresholding operation. This operation procedure is suited for the design of an array processor, because it can be recursively and repeatedly executed. Systolic array circuit architecture with Residue Number System is suggested to realize the efficient arithmetic circuit for matrix-vector multiplication and compute sigmoid function. The proposed design method would expect to adopt for the application field of neural networks, because it can be realized to currently developed VLSI technology.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.570-574
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• 1990

Detection of left ventricular boundary for the functional analysis of LV(left ventricle)is obtained using automatic boundary detection algorithm based on dynamic programming method. This scheme reduces the edge searching time and ensures connective edge detection, since it does not require general edge operator, edge thresholding and linking process of other edge. detection methods. The left ventricular diastolic volume and systolic volume and systolic volume were computed after this automatic boundary detection, and these Volume data wm applied to analyze LV ejection fraction.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.165-167
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• 1988

In this paper, the design of decoder for R-S code using discrete finite-field Fourier transform is presented. An important ingredient of this design is a modified Euclid algorithm for computing the error-locator polynomial. The computation of inverse elements is completely avoided in this modification of Euclid algorithm. This decoder is regular and simple, and naturally suitable for VLSI implementation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.24-31
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• 1998

This paper presents a pipeline high-level synthesis tool for designing trace-back systolic array viterbi decoder. It consists of a dta flow graph(DFG) generator and a pipeline data path synthesis tool. First, the DFG of the vitrebi decoder is generated in the from of VHDL netlist. The inputs to the DFG generator are parameters of the convolution encoder. Next, the pipeline scheduling and allocationare performed. The synthesis tool explores the design space efficiently, synthesizes various designs which meet the given constraints, and choose the best one.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.1
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• pp.39-52
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• 1998

본 논문에서는 모듈러 지수승시에 요구되는 모듈러 곱셈의 반복 횟수를 줄이기 위해 SM(m)기법을 제안하며 지수를 SM(m)표현과 시스톨릭 SM(m) 표현으로 변환한다.그리고 변환된 스스톨릭 SM(m) 표현으로부터 모듈러 지수연산을 위한 선형시스톨릭 어레이를 제시한다. 제안된 기법은 기존의 방법보다 소프트웨어로 구현시에 선 계산기에 필요한 기업 장소의 크기를 줄였으며, 선형 시스톨릭 어레이로 구현시에 기존의 방법들보다 처리기의 개수를 감소시키며, 처리기내에 필요한 기억 장소의 크기를 줄였다. 수정된 부호화 디지트 기법과 비교하면 처리기의 개수를 24%정도 줄일 수 있다.

• Journal of Acupuncture Research
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• v.23 no.4
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• pp.49-60
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• 2006

Objectives : The aim of the study was to investigate the antihypertensive effect of Gyeok pal sang saeng Yeok chim Acupuncture in hypertensive patients. Methods : We measured the blood pressure of the patients who were admitted in the Oriental Medical Clinic of Brother from 13th February 2006 to 13th May 2006. We included the patients only in case of the systolic blood pressure was over 120mmHg or diastolic blood pressure was over 80mmHg, thirty patients were treated by Gyeok pal sang saeng Yeok chim Acupuncture. In order to evaluate the effect of the Gyeok pal sang saeng Yeok chim Acupuncture, the blood pressure and pulse rate were measured before and after Acupuncture procedure total 10 times. Results : There were significant decrease in the systolic blood pressure and significant decrease in the diastolic blood pressure treated by Gyeok pal sang saeng Yeok chim Acupuncture 10 times but pulse rate was not significantly decreased. The effect of Gyeok pal sang saeng Yeok chim Acupuncture by measurement time on blood pressure were follows: In a systolic blood pressure and diastolic blood pressure was gradually deceased significantly from 1st to 10th but pulse rate was not significantly decreased. Conclusion : These results suggest that Gyeok pal sang saeng Yeok chim Acupuncture is effective in decreasing the systolic and diastolic blood pressure.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.37-43
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• 2020

In this paper, we propose an efficient AB² multiplication algorithm using SPB(shifted polynomial basis) over finite fields. Using the feature of the SPB, we split the equation for AB² multiplication into two parts. The two partitioned equations are executable at the same time, and we derive an algorithm that processes them in parallel. Then we propose an efficient semi-systolic AB² multiplier based on the proposed algorithm. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the proposed AB² multiplier saves about 94%, 87%, 86% and 83% of the AT complexity of the multipliers of Wei, Wang-Guo, Kim-Lee, Choi-Lee, respectively. Therefore, the proposed multiplier is suitable for VLSI implementation and can be easily adopted as the basic building block for various applications.